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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20100296330A1

    公开(公告)日：2010-11-25

    申请号：US12777353

    申请日：2010-05-11

    申请人： Hiroshi KOTAKI ,  Yoshiji Ohta ,  Syuji Wakaiki

    发明人： Hiroshi KOTAKI ,  Yoshiji Ohta ,  Syuji Wakaiki

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C5/14

    CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/79 ,  G11C2213/82

    摘要： There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.

    摘要翻译： 提供了能够抑制写入干扰而不增加单元阵列区域的半导体存储器件。 半导体存储器件具有存储单元阵列，其中具有双端型存储元件的多个存储单元和串联连接的选择晶体管以矩阵形式排列;第一施加电压施加电压脉冲， 第一位线和第二电压施加电路，用于将预充电电压施加到第一和第二位线，使得在写入存储器单元时，第一电压施加电路对两端进行预充电 ，然后第二电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲以进行选择。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08139395B2

    公开(公告)日：2012-03-20

    申请号：US12777353

    申请日：2010-05-11

    申请人： Hiroshi Kotaki ,  Yoshiji Ohta ,  Syuji Wakaiki

    发明人： Hiroshi Kotaki ,  Yoshiji Ohta ,  Syuji Wakaiki

    IPC分类号： G11C11/00

    CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/79 ,  G11C2213/82

    摘要： There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.

    摘要翻译： 提供了能够抑制写入干扰而不增加单元阵列区域的半导体存储器件。 半导体存储器件具有存储单元阵列，其中具有两端型存储元件的数量的存储单元和串联连接的选择晶体管以矩阵形状排列;第一施加电压电路，用于将写入电压脉冲施加到 第一位线和第二电压施加电路，用于向第一和第二位线施加预充电电压，使得在写入存储单元时，第一电压施加电路对两端进行预充电 ，然后第二电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲以进行选择。

    Semiconductor device, liquid crystal display device and electronic equipment
    4.
    发明授权
    Semiconductor device, liquid crystal display device and electronic equipment 有权
    半导体装置，液晶显示装置及电子设备

    公开(公告)号：US07804705B2

    公开(公告)日：2010-09-28

    申请号：US12022785

    申请日：2008-01-30

    申请人： Hiroshi Iwata ,  Yoshiji Ohta

    发明人： Hiroshi Iwata ,  Yoshiji Ohta

    IPC分类号： G11C11/00

    CPC分类号： G09G3/3648 ,  G09G2300/0809 ,  G09G2320/0214

    摘要： The semiconductor device of the present invention has a circuit block in which m (m is an integer of not smaller than two) sets of first through m-th transistor columns where two or more transistors are connected in series, one terminal of the first through m-th transistor columns is connected to a first output node, and the other terminal of the first through m-th transistor columns is connected to a second output node. A control signal for substantially simultaneously turning on and off all the transistors of the first through m-th transistor columns is inputted to the control input terminals of the transistors of the first through m-th transistor columns.

    摘要翻译： 本发明的半导体器件具有其中两个或多个晶体管串联连接的第一至第m晶体管列的m（m为不小于2的整数）的电路块，第一至第 第m晶体管列连接到第一输出节点，第一至第m晶体管列的另一端连接到第二输出节点。 用于基本上同时导通和关断第一至第m晶体管列的所有晶体管的控制信号被输入到第一至第三晶体管列的晶体管的控制输入端。

    Group robot system that can obtain detailed overall information of object efficiently
    5.
    发明授权
    Group robot system that can obtain detailed overall information of object efficiently 有权
    组织机器人系统可以有效获取对象的详细总体信息

    公开(公告)号：US07409266B2

    公开(公告)日：2008-08-05

    申请号：US10739453

    申请日：2003-12-17

    申请人： Keita Hara ,  Masaki Hamamoto ,  Yoshiji Ohta

    发明人： Keita Hara ,  Masaki Hamamoto ,  Yoshiji Ohta

    IPC分类号： G06F19/00

    CPC分类号： G06N3/008 ,  B64C33/025 ,  B64C2201/025 ,  B64C2201/143 ,  G05D1/104

    摘要： A group robot system includes a plurality of sensing robots and a base station controlling the sensing robots, and establishes communication in a hierarchical manner. The hierarchical structure is formed of a plurality of levels between a plurality of sensing robots with base station as the highest hierarchical level. The first sensing robot detects an object; the second sensing robot conducts further search on the object; and the third sensing robot conducts communication relay between the first sensing robot and the base station. When the first sensing robot detects an object, the base station provides control such that all sensing robots, other than the first, second and third sensing robots, move outside the current area of search.

    摘要翻译： 组机器人系统包括多个感测机器人和控制感测机器人的基站，并以层次的方式建立通信。 层次结构由具有基站的多个感测机器人之间的多个级别形成为最高层级。 第一感测机器人检测物体; 第二感测机器人进一步搜索物体; 并且第三感测机器人在第一感测机器人和基站之间进行通信中继。 当第一感测机器人检测到物体时，基站提供控制，使得除了第一，第二和第三感测机器人之外的所有感测机器人移动到当前搜索区域之外。

    Semiconductor storage device and electronic equipment
    6.
    发明授权
    Semiconductor storage device and electronic equipment 有权
    半导体存储设备和电子设备

    公开(公告)号：US07385848B2

    公开(公告)日：2008-06-10

    申请号：US11516642

    申请日：2006-09-07

    申请人： Hiroshi Iwata ,  Yoshiji Ohta

    发明人： Hiroshi Iwata ,  Yoshiji Ohta

    IPC分类号： G11C11/34

    CPC分类号： G11C7/12 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/28 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/7923

    摘要： A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section. Each memory cell has two storage regions in vicinity of opposite ends of a channel region, first and second input/output terminals, and a control terminal. The readout section reads information stored in one of the first and second storage regions of a memory cell based on a first output equivalent to an output current from the memory cell when a current is passed from the first input/output terminal to the second input/output terminal of the memory cell and a second output equivalent to an output current from the memory cell when a current is passed from the second input/output terminal to the first input/output terminal.

    摘要翻译： 半导体存储装置具有由多个阵列存储单元，字线，位线，位线充电和放电电路和读出部组成的存储单元阵列。 每个存储单元在通道区域的相对端附近具有两个存储区域，第一和第二输入/输出端子以及控制端子。 当电流从第一输入/输出端子传递到第二输入/输出端时，读出部分基于与来自存储器单元的输出电流相当的第一输出读取存储在存储单元的第一和第二存储区域之一中的信息。 输出端子和当电流从第二输入/输出端子传递到第一输入/输出端子时相当于来自存储器单元的输出电流的第二输出。

    Flapping apparatus
    7.
    发明授权
    Flapping apparatus 有权
    拍打装置

    公开(公告)号：US07195199B2

    公开(公告)日：2007-03-27

    申请号：US11107064

    申请日：2005-04-15

    申请人： Yoshiji Ohta ,  Keita Hara ,  Masaki Hamamoto

    发明人： Yoshiji Ohta ,  Keita Hara ,  Masaki Hamamoto

    IPC分类号： B64C33/00

    CPC分类号： B64C33/02

    摘要： A flapping apparatus includes a first disk rotated by a driving source, and a second disk that rotates in contact with a main surface of the first disk. The second disk is provided with first and second stoppers that limit its angle of rotation. When the stopper is in contact with the first disk, rotation of a wing shaft is caused only by the rotation of the first disk, and when the stoppers are not in contact with the first disk, rotation of the wing shaft is caused only by the rotation of the second disk.

    摘要翻译： 拍打装置包括由驱动源旋转的第一盘和与第一盘的主表面接触旋转的第二盘。 第二盘设置有限制其旋转角度的第一和第二挡块。 当止动件与第一盘接触时，翼轴的旋转仅由第一盘的旋转引起，并且当止动件不与第一盘接触时，翼轴的旋转仅由 旋转第二盘。

    Semiconductor storage device capable of accurately collectively executing erase verify operation on all memory cells
    8.
    发明授权
    Semiconductor storage device capable of accurately collectively executing erase verify operation on all memory cells 失效
    半导体存储装置能够对所有存储单元进行精确的集体执行擦除验证动作

    公开(公告)号：US6081452A

    公开(公告)日：2000-06-27

    申请号：US25996

    申请日：1998-02-19

    申请人： Yoshiji Ohta

    发明人： Yoshiji Ohta

    IPC分类号： G11C16/02 ,  G11C8/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34

    CPC分类号： G11C16/3445 ,  G11C16/344 ,  G11C8/10 ,  G11C2216/28

    摘要： A verify operation is accurately collectively executed on all memory cells. In verify operation, first, the levels of a pre-charge signal .phi.pre and a collective erase verify mode selection signal .phi.aev are made to be "L", so that a common bit line 5 and all bit lines BL0 through BLm are individually charged with a pre-charge voltage Vpre. Thereafter, the level of the collective erase verify mode selection signal .phi.aev is made to be "H" to connect the common bit line 5 to all the bit lines BL0 through BLm and a sense amplifier 8, and all word lines WL0 through WLn are selected by a row decoder circuit 2. Then, there is watched an event that the common bit line 5 is discharged and an output signal OUT of the sense amplifier 8 becomes "L" due to the existence of a non-erased memory cell in a memory cell array 1. In this case, the discharge of the common bit line 5 occurs when at least one non-erased memory cell transistor MT exists in the memory cell array 1, and therefore, the verify operation can be accurately collectively executed on all the memory cells.

    摘要翻译： 在所有存储单元上精确地执行验证操作。 在验证操作中，首先，使预充电信号phi pre和集体擦除验证模式选择信号phi的电平为“L”，使得公共位线5和所有位线BL0至BLm分别 带有预充电电压Vpre。 此后，集体擦除验证模式选择信号phi aev的电平为“H”，以将公共位线5连接到全部位线BL0至BLm和读出放大器8，并且所有字线WL0至WLn均为 然后，由于存在一个未擦除的存储单元，观察到公共位线5被放电的事件和读出放大器8的输出信号OUT变为“L” 在这种情况下，当在存储单元阵列1中存在至少一个未擦除的存储单元晶体管MT时，发生公共位线5的放电，因此，可以全面地准确地执行验证操作 记忆细胞。