公开(公告)号：US20140042695A1

公开(公告)日：2014-02-13

申请号：US13755624

申请日：2013-01-31

申请人： Hiroshi MAEJIMA ,  Hiroto AKIYAMA

发明人： Hiroshi MAEJIMA ,  Hiroto AKIYAMA

IPC分类号： B65H29/14

CPC分类号： B65H29/14 ,  B65H9/101 ,  B65H29/34 ,  B65H31/10 ,  B65H31/20 ,  B65H31/3027 ,  B65H31/34 ,  B65H31/38 ,  B65H2301/4212 ,  B65H2301/4213 ,  B65H2403/411 ,  B65H2404/1521 ,  B65H2404/1523 ,  B65H2404/166 ,  B65H2404/232 ,  B65H2404/242 ,  B65H2404/731 ,  B65H2404/742 ,  B65H2553/612 ,  B65H2553/83 ,  B65H2801/27

摘要： To provide a post-processing apparatus for preventing a sheet from becoming misaligned in dropping the rear end side of the sheet carried in a processing tray from a sheet discharge path to store on the tray, and enabling the mechanism to be simplified, compact and configured at low cost, a sheet guide that guides a sheet from the sheet discharge path to the processing tray is comprised of a pair of right and left guide members, at the same time in the processing tray are disposed a pair of right and left side edge alignment members, and each guide member and each side edge alignment member are configured to shift to positions in the sheet width direction in an integral manner using a common drive motor.

摘要翻译： 为了提供一种后处理装置，用于防止片材在从处理托盘中携带的片材的后端侧从片材排出路径落下而不能对准以存储在托盘上，并且使得该机构能够被简化，紧凑和配置 以低成本，将片材从片材排出路径引导到处理托盘的片材引导件由一对左右引导构件构成，并且在处理托盘中同时设置有一对左右侧边缘 对准构件，并且每个引导构件和每个侧边对准构件被构造成使用公共驱动马达以一体的方式移动到片材宽度方向上的位置。

公开(公告)号：US20120320678A1

公开(公告)日：2012-12-20

申请号：US13424724

申请日：2012-03-20

申请人： Hiroshi MAEJIMA ,  Natsuki Sakaguchi

发明人： Hiroshi MAEJIMA ,  Natsuki Sakaguchi

IPC分类号： G11C16/28 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/28 ,  H01L27/11582

摘要： In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

摘要翻译： 在执行存储晶体管的读取操作时，控制电路向连接到所选择的存储晶体管的选定字线提供第一电压。 第二电压被提供给连接到除所选存储晶体管之外的非选择存储晶体管的未选择字线，第二电压高于第一电压。 第三电压被提供给位线。 在源极线之间提供低于第三电压的第四电压，所选择的源极线连接到包括选择的存储器块中的所选择的存储晶体管的存储器串。 在源极线中，提供与第三电压基本相同的第五电压，所述未选择的源极线连接到所选择的存储器块中的未选择的存储器串。

公开(公告)号：US20120044750A1

公开(公告)日：2012-02-23

申请号：US13284136

申请日：2011-10-28

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C11/00

CPC分类号： G11C13/0021 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0088 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101

摘要： A semiconductor memory device includes a cell array having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between the plurality of first wirings and the plurality of second wirings. The semiconductor memory device further includes a control circuit for selectively driving the plurality of first wirings and the plurality of second wirings. The control circuit applies a first voltage for a first operation to a first select wiring and applies a second voltage for a second operation different from the first operation to a second select wiring and applies a third voltage for the first and second operation to a third select wiring. The first operation is completed before the second operation is completed. The control circuit applies a fourth voltage for a third operation to a forth select wiring before the second operation is completed.

摘要翻译： 半导体存储器件包括具有多条第一布线和多条彼此交叉的第二布线的单元阵列以及设置在该多条第一布线与该多条第二布线之间的交叉处的存储单元。 半导体存储器件还包括用于选择性地驱动多个第一布线和多个第二布线的控制电路。 控制电路将第一操作的第一电压施加到第一选择布线，并将与第一操作不同的第二操作的第二电压施加到第二选择布线，并将第一和第二操作的第三电压施加到第三选择 接线。 第一次操作在第二次操作完成之前完成。 在第二操作完成之前，控制电路将用于第三操作的第四电压施加到第四选择布线。

公开(公告)号：US20110128775A1

公开(公告)日：2011-06-02

申请号：US13024926

申请日：2011-02-10

申请人： Hiroshi MAEJIMA ,  Katsuaki Isobe ,  Hideo Mukai

发明人： Hiroshi MAEJIMA ,  Katsuaki Isobe ,  Hideo Mukai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C7/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.

摘要翻译： 非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。 控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器 和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压， 选择第二根线。

公开(公告)号：US20110069550A1

公开(公告)日：2011-03-24

申请号：US12953690

申请日：2010-11-24

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3422

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

摘要翻译： 根据本发明的示例的三维堆叠的非易失性半导体存储器包括由第一和第二块组成的存储单元阵列。 第一块具有第一单元单元，其包括要编程的存储器单元和不包括要编程的存储单元的第二单元单元，并且通过将程序电位或转移电位施加到 在第一和第二单元单元中的存储器单元的通道的初始电位被设置为正电位之后的第一块。 在编程中，程序电位和转移电位不适用于第二个程序段中的字线。

公开(公告)号：US20100110799A1

公开(公告)日：2010-05-06

申请号：US12650981

申请日：2009-12-31

申请人： Makoto HAMADA ,  Hiroshi MAEJIMA

发明人： Makoto HAMADA ,  Hiroshi MAEJIMA

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/34

摘要： A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell.

摘要翻译： 一种非易失性半导体存储器件，其能够通过将源极线和阱线偏置为正电压来读取和验证负阈值电池。 非易失性半导体存储器件包括预充电电路，该预充电电路在读取和验证负阈值单元时将位线预充电到与源极线相同的电压。

公开(公告)号：US20100097127A1

公开(公告)日：2010-04-22

申请号：US12646531

申请日：2009-12-23

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G05F1/10 ,  H03K3/01

CPC分类号： H02M3/07

摘要： A voltage supply circuit includes a booster circuit and a ripple filter circuit. The ripple filter circuit has a first resistor connected to a first output terminal at one end thereof. The ripple filter circuit also has a first switch circuit connected between the other end of the first resistor and a second output terminal. In addition, the ripple filter circuit has a second switch circuit connected between the first output terminal of the booster circuit and the first switch circuit.

摘要翻译： 电压电路包括升压电路和纹波滤波电路。 波纹滤波器电路具有在其一端连接到第一输出端的第一电阻。 波纹滤波器电路还具有连接在第一电阻器的另一端和第二输出端子之间的第一开关电路。 此外，纹波滤波器电路具有连接在升压电路的第一输出端子和第一开关电路之间的第二开关电路。

公开(公告)号：US20090244968A1

公开(公告)日：2009-10-01

申请号：US12406477

申请日：2009-03-18

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26

摘要： A semiconductor memory device includes a select transistor, a memory cell transistor, a select gate line, a word line, and a row decoder. The memory cell transistor includes a charge accumulation layer and a control gate, and a current path one end of which is connected to a current path in the select transistor. The select gate line and word line are connected to a gate and the control gate of the select transistor and memory cell transistor. The row decoder includes a transfer circuit which transfers a voltage to the select gate line and includes a first switch including a first MOS transistor of a depression type. The first MOS transistor includes a current path one end of which is connected to the select gate line, and transfers a first voltage provided to the other end of the current path to the select gate line.

摘要翻译： 半导体存储器件包括选择晶体管，存储单元晶体管，选择栅极线，字线和行解码器。 存储单元晶体管包括电荷累积层和控制栅极，并且其电流路径的一端连接到选择晶体管中的电流路径。 选择栅极线和字线连接到选通晶体管和存储单元晶体管的栅极和控制栅极。 行解码器包括传送电路，其将电压传送到选择栅极线，并且包括具有凹陷型的第一MOS晶体管的第一开关。 第一MOS晶体管包括电流路径，其一端连接到选择栅极线，并将提供给电流路径的另一端的第一电压传送到选择栅极线。

公开(公告)号：US20090244953A1

公开(公告)日：2009-10-01

申请号：US12401200

申请日：2009-03-10

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C11/00 ,  G11C11/416 ,  G11C7/10 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a data write circuit operative to apply a voltage required for data write to the memory cell via the first and second lines; and a current limit circuit operative to limit the value of current flowing in the memory cell on the data write at a certain current limit value.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，其包括第一和第二相交线以及布置在第一和第二线的交点处的电可擦除可编程存储单元，每个存储单元包含可变电阻元件; 数据写入电路，用于经由第一和第二行向存储器单元施加数据写入所需的电压; 以及电流限制电路，其操作以在一定电流极限值下限制在所述存储器单元中流动的数据写入数据的电流值。

公开(公告)号：US20090174032A1

公开(公告)日：2009-07-09

申请号：US12351212

申请日：2009-01-09

申请人： Hiroshi MAEJIMA ,  Katsuaki Isobe ,  Hideo Mukai

发明人： Hiroshi MAEJIMA ,  Katsuaki Isobe ,  Hideo Mukai

IPC分类号： H01L29/00

CPC分类号： G11C13/00 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/24

摘要： A resistance change memory device includes: a semiconductor substrate; a three dimensional cell array formed by a plurality of unit cell array blocks of two dimensional arrangement on the semiconductor substrate, the unit cell array block being formed by stacking a plurality of unit cell arrays including a first wiring, a second wiring crossing with the first wiring, and a variable resistance element connected at an intersection of the both wirings; a reading/writing/driving circuit formed on the semiconductor substrate under the three dimensional cell array; a first via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the first wiring in each layer to the reading/writing/driving circuit is formed; and a second via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the second wiring in each layer to the reading/writing/driving circuit is formed. When the first wiring is longer than the second wiring, the number of via arrangements in the first via region is set larger than that in the second via region.

摘要翻译： 电阻变化存储器件包括：半导体衬底; 由半导体衬底上的二维排列的多个单元阵列块形成的三维单元阵列，所述单元阵列块通过堆叠多个单元阵列而形成，所述单位阵列包括第一布线，与所述第一布线交叉的第二布线 布线和连接在两条布线的交点处的可变电阻元件; 在三维单元阵列下形成在半导体衬底上的读/写/驱动电路; 布置在单元阵列块的端部中的第一通孔区域，其中形成用于将每层中的第一布线连接到读/写/驱动电路的通孔布线; 以及布置在单元阵列块的端部中的第二通孔区域，并且其中形成用于将每层中的第二布线连接到读/写/驱动电路的通孔布线。 当第一布线长于第二布线时，第一通孔区域中的通孔布置的数量被设置为大于第二通孔区域中的通孔布置的数量。