公开(公告)号：US20130078787A1

公开(公告)日：2013-03-28

申请号：US13702758

申请日：2011-05-16

申请人： Hiroshi Nakatsuji ,  Kazushige Hotta ,  Naoki Makita

发明人： Hiroshi Nakatsuji ,  Kazushige Hotta ,  Naoki Makita

IPC分类号： H01L21/04

CPC分类号： H01L27/1288 ,  H01L21/04 ,  H01L27/1214

摘要： Disclosed is a method for manufacturing a semiconductor device, including the steps of: forming a first semiconductor film (2) and a second semiconductor film (4) over a glass substrate (6); forming a photosensitive resin over the glass substrate (6) to cover the first semiconductor film (2) and the second semiconductor film (4); conducting an exposure process in which controlled amounts of exposure radiation are projected to the photosensitive resin using a photomask; conducting a developing process on the photosensitive resin that was subjected to the exposure process, to form a first resist (40) over the first semiconductor film (2) and to form a second resist (41) over the second semiconductor film (4); implanting an n-type impurity into the first semiconductor film (2) using the first resist (40) and the second resist (41) as masks; and removing the first resist (40) and implanting a p-type impurity into the first semiconductor film (2) using the second resist (41) as a mask.

摘要翻译： 本发明公开了一种半导体器件的制造方法，包括以下步骤：在玻璃基板（6）上形成第一半导体膜（2）和第二半导体膜（4）。 在所述玻璃基板（6）上形成感光性树脂以覆盖所述第一半导体膜（2）和所述第二半导体膜（4）。 进行使用光掩模将受控量的曝光辐射投射到感光性树脂的曝光处理; 对经过曝光处理的感光性树脂进行显影处理，在第一半导体膜（2）上形成第一抗蚀剂（40），并在第二半导体膜（4）上形成第二抗蚀剂（41）。 使用第一抗蚀剂（40）和第二抗蚀剂（41）作为掩模将n型杂质注入到第一半导体膜（2）中; 并使用第二抗蚀剂（41）作为掩模，去除第一抗蚀剂（40）并将p型杂质注入到第一半导体膜（2）中。

公开(公告)号：US07859078B2

公开(公告)日：2010-12-28

申请号：US12414273

申请日：2009-03-30

申请人： Kazushige Hotta

发明人： Kazushige Hotta

IPC分类号： H01L21/70

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/4908 ,  H01L29/78621

摘要： A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.

摘要翻译： 形成第一绝缘膜。 然后，在第一绝缘膜上形成有用于覆盖构成高电压驱动薄膜晶体管的沟道的区域的低电压驱动薄膜晶体管的栅电极和掩模膜。 在使用栅电极和掩模膜作为掩模的同时将杂质注入到半导体膜中，从而形成高浓度杂质区。 此后，通过在例如500℃的条件下进行热处理2小时使该杂质活化。 随后，去除掩模膜并形成第二绝缘膜。 高电压驱动薄膜晶体管的栅电极在第二绝缘膜上形成有铝合金。

公开(公告)号：US07619288B2

公开(公告)日：2009-11-17

申请号：US11886147

申请日：2006-05-16

申请人： Kazushige Hotta

发明人： Kazushige Hotta

IPC分类号： H01L27/088

CPC分类号： H01L27/127 ,  G02F1/1362 ,  G09G3/006 ,  G09G3/3648 ,  G09G2330/04 ,  H01L27/1214 ,  H01L29/78621 ,  H01L29/78627

摘要： A method for manufacturing a thin film transistor substrate includes a step of forming a plurality of island-like semiconductor films above an insulating transparent substrate; a step of forming a gate insulating film on each of the island-like semiconductor films; a step of forming first conductivity type LDD regions on both sides in the first island-like semiconductor film by leaving a channel region and forming a first conductivity type normally-on channel region having an impurity density equivalent to that of the LDD region in the second island-like semiconductor film; a step of forming a first gate electrode partially covering the LDD region and forming a second gate electrode above the normally-on channel region, and a step of forming a first conductivity type source/drain region having an impurity density higher than that of the LDD region in regions on the both sides of the gate electrode.

摘要翻译： 制造薄膜晶体管基板的方法包括在绝缘性透明基板的上方形成多个岛状半导体膜的工序; 在每个岛状半导体膜上形成栅绝缘膜的步骤; 在第一岛状半导体膜的两侧形成第一导电型LDD区，通过留下沟道区并形成具有与第二导电型LDD区相同的第一导电型正常导通型沟道区的步骤 岛状半导体膜; 形成部分地覆盖LDD区域并在正常通道区域上形成第二栅电极的第一栅电极的步骤，以及形成杂质密度高于LDD的第一导电型源/漏区的步骤 区域在栅电极的两侧的区域中。

公开(公告)号：US07535065B2

公开(公告)日：2009-05-19

申请号：US11025797

申请日：2004-12-29

申请人： Kazushige Hotta

发明人： Kazushige Hotta

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/4908 ,  H01L29/78621

摘要： A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.

摘要翻译： 形成第一绝缘膜。 然后，在第一绝缘膜上形成有用于覆盖构成高电压驱动薄膜晶体管的沟道的区域的低电压驱动薄膜晶体管的栅电极和掩模膜。 在使用栅电极和掩模膜作为掩模的同时将杂质注入到半导体膜中，从而形成高浓度杂质区。 此后，通过在例如500℃的条件下进行热处理2小时使该杂质活化。 随后，去除掩模膜并形成第二绝缘膜。 高电压驱动薄膜晶体管的栅电极在第二绝缘膜上形成有铝合金。

公开(公告)号：US07189603B2

公开(公告)日：2007-03-13

申请号：US11226539

申请日：2005-09-14

申请人： Kazushige Hotta

发明人： Kazushige Hotta

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

摘要： A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is fomed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold voltage for p-channel TFT. A second gate electrode layer is formed and patterned to form second gate electrodes. By using the first gate electrode layer as a mask, boron ions are implanted at a high concentration to form source/drain regions of the p-channel TFT. By using the second gate electrodes as a mask, the first gate electrode layer is etched to form gate electrodes. Phosphorous ions are implanted at a low concentration to form LDD regions. By using a fourth mask, P ions are implanted at a high concentration to form source/drain regions of n-channel TFTs.

摘要翻译： 形成具有用于n沟道的阈值电压的半导体层并将其图案化到TFT岛区域。 沉积栅极绝缘膜。 第一栅极电极层被发射和图案化以形成开口。 将磷离子注入开口中的p沟道TFT，以设置p沟道TFT的阈值电压。 形成第二栅极电极层并构图以形成第二栅电极。 通过使用第一栅极电极层作为掩模，以高浓度注入硼离子以形成p沟道TFT的源极/漏极区域。 通过使用第二栅电极作为掩模，蚀刻第一栅电极层以形成栅电极。 以低浓度注入磷离子以形成LDD区。 通过使用第四掩模，以高浓度注入P离子以形成n沟道TFT的源/漏区。

公开(公告)号：US20060289870A1

公开(公告)日：2006-12-28

申请号：US11385077

申请日：2006-03-21

申请人： Kazushige Hotta ,  Takuya Hirano

发明人： Kazushige Hotta ,  Takuya Hirano

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13454 ,  H01L27/1285 ,  H01L29/04

摘要： A method for producing a thin film transistor substrate includes the steps of: (i) depositing an amorphous semiconductor film on a transparent insulating substrate; (ii) patterning the amorphous semiconductor film so as to form insular amorphous semiconductor films, the step (ii) including a process (I) for forming, in respective stripe areas each of which is elongate in a first direction in a display area, a plurality of insular semiconductor films whose channel length is in line with the first direction, and a process (II) for forming, in an area including extended portions of the striped areas in a peripheral circuit area, a plurality of insular semiconductor films; (iii) polycrystallizing the insular semiconductor films in the peripheral circuit area so that the insular semiconductor films have high mobility in a second direction and polycrystallizing the insular semiconductor films in the display area so that the insular semiconductor films have high mobility in the first direction; and (iv) forming TFTs by using polycrystalline insular semiconductor films. In at least one peripheral circuit, a channel of a high speed TFT is positioned on a portion other than the extended portions of the stripe areas.

摘要翻译： 一种制造薄膜晶体管基板的方法包括以下步骤：（i）在透明绝缘基板上沉积非晶半导体膜; （ii）对非晶半导体膜进行图形化以形成非晶半导体非晶半导体膜，步骤（ii）包括在显示区域中沿着第一方向细长的各个条带区域中形成用于形成的工序（I）， 多个岛状半导体膜，其通道长度与第一方向一致;以及在包括外围电路区域中的条纹区域的延伸部分的区域中形成多个岛状半导体膜的工艺（II） （iii）使外围电路区域中的岛状半导体膜多晶化，使得岛状半导体膜在第二方向上具有高迁移率，并使显示区域中的岛状半导体膜多晶化，使得岛状半导体膜在第一方向上具有高迁移率; 和（iv）通过使用多晶的半导体膜形成TFT。 在至少一个外围电路中，高速TFT的通道位于除了区域的延伸部分之外的部分上。

公开(公告)号：US20050255621A1

公开(公告)日：2005-11-17

申请号：US11183383

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

公开(公告)号：US20050250264A1

公开(公告)日：2005-11-10

申请号：US11183432

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

摘要翻译： 在玻璃基板上的预定区域中形成多晶硅膜，然后在其上形成宽度比栅极绝缘膜窄的栅极绝缘膜和栅极电极。 然后，在整个表面上形成层间绝缘膜和ITO膜。 然后，通过将n型杂质注入多晶硅膜形成具有LDD结构的n型源/漏区。 然后，用抗蚀剂膜覆盖n型TFT形成区域和像素电极形成区域，然后通过以p型将p型杂质注入多晶硅膜形成p型源极/漏极区域 TFT形成区域。 然后，抗蚀剂膜仅留在像素电极形成区域中，并且抗蚀剂膜从其它区域去除。 通过在使用剩余的抗蚀剂膜作为掩模的同时蚀刻ITO膜来形成像素电极。

公开(公告)号：US06939750B2

公开(公告)日：2005-09-06

申请号：US10839643

申请日：2004-05-05

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

公开(公告)号：US20050161673A1

公开(公告)日：2005-07-28

申请号：US11087152

申请日：2005-03-23

申请人： Seiji Doi ,  Kazushige Hotta ,  Takuya Hirano ,  Kenichi Yanai

发明人： Seiji Doi ,  Kazushige Hotta ,  Takuya Hirano ,  Kenichi Yanai

IPC分类号： G02F1/1368 ,  G02F1/136 ,  G02F1/1362 ,  G09F9/00 ,  G09F9/30 ,  G09F9/35 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L27/1288 ,  G02F1/13454 ,  H01L27/1214 ,  H01L27/1237 ,  H01L27/127 ,  H01L29/42384

摘要： The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.

摘要翻译： 本发明涉及形成在液晶显示装置等的绝缘基板上的薄膜晶体管装置及其制造方法以及液晶显示装置。 在结构上，提供了在用于覆盖第一岛状半导体膜的第一绝缘膜上形成负性光致抗蚀剂膜的步骤，形成相对于第一岛状半导体膜的周边在内部区域具有开口部的抗蚀剂掩模 通过从透明基板的背面侧曝光/显影负性光致抗蚀剂膜，蚀刻抗蚀剂掩模的开口部分中的第一绝缘膜，形成用于覆盖第一绝缘膜的第二绝缘膜和 导电膜，并且通过图案化导电膜形成第一栅电极和第二栅电极。