公开(公告)号：US11870212B2

公开(公告)日：2024-01-09

申请号：US16963054

申请日：2018-03-28

Applicant: Mitsubishi Electric Corporation

Inventor： Kazumasa Kishimoto ,  Naoki Nakamura

IPC: H01S5/02 ,  H01S5/042 ,  H01S5/12 ,  H01S5/227 ,  H01S5/22 ,  H01S5/028

CPC classification number: H01S5/0208 ,  H01S5/04256 ,  H01S5/04257 ,  H01S5/12 ,  H01S5/2275 ,  H01S5/0283 ,  H01S5/2224

Abstract: A mesa (34) includes a resonator and a second conductivity type contact layer (24). Grooves (32) are provided on both sides of the mesa (34). The first conductivity type contact layer (12) and a side face of the mesa (34) including an end face of the resonator construct an L shape (50). The first conductivity type contact layer (12) constructs bottom surfaces of the L shape (50) and the grooves (32). A side face of the groove (32) includes a slope (38) near the bottom surface (46) and a side face (42) above. A side face of the L shape (50) includes a slope (40) near the bottom surface (48) and a side face (44) above. A first electrode (28) is connected to the first conductivity type contact layer (12) at the bottom surface (46) of the groove (32). A second electrode (30) is connected to the second conductivity type contact layer (24) above the mesa (34).

公开(公告)号：US11728625B2

公开(公告)日：2023-08-15

申请号：US16956376

申请日：2018-12-11

Applicant: Sony Corporation

Inventor： Tatsushi Hamaguchi ,  Jugo Mitomo ,  Rintaro Koda

IPC: H01S5/183 ,  H01S5/343 ,  H01S5/02 ,  H01S5/042

CPC classification number: H01S5/34333 ,  H01S5/0206 ,  H01S5/0207 ,  H01S5/0208 ,  H01S5/04257 ,  H01S5/18361

Abstract: A light emitting element of the present disclosure includes a compound semiconductor substrate 11, a stacked structure 20 including a GaN-based compound semiconductor, a first light reflection layer 41, and a second light reflection layer 42. The stacked structure 20 includes, in a stacked state a first compound semiconductor layer 21, an active layer 23, and a second compound semiconductor layer 22. The first light reflection layer 41 is disposed on the compound semiconductor substrate 11 and has a concave mirror section 43. The second light reflection layer 42 is disposed on a second surface side of the second compound semiconductor layer 22 and has a flat shape. The compound semiconductor substrate 11 includes a low impurity concentration compound semiconductor substrate or a semi-insulating compound semiconductor substrate.

公开(公告)号：US20180366909A1

公开(公告)日：2018-12-20

申请号：US15996562

申请日：2018-06-04

Applicant: Oclaro Japan, Inc.

Inventor： Takeshi KITATANI ,  Kaoru OKAMOTO ,  Kouji NAKAHARA

IPC: H01S5/30 ,  H01L31/105 ,  H01L31/0304 ,  H01L31/18 ,  H01S5/02 ,  H01S5/026 ,  H01S5/22 ,  H01S5/343 ,  H01S5/042

CPC classification number: H01S5/3054 ,  H01L31/03046 ,  H01L31/105 ,  H01L31/1844 ,  H01S5/0208 ,  H01S5/026 ,  H01S5/0425 ,  H01S5/22 ,  H01S5/3432 ,  H04B10/40

Abstract: An optical semiconductor device includes an InP substrate; an active layer disposed above the InP substrate; a n-type semiconductor layer disposed below the active layer; and a p-type clad layer disposed above the active layer, wherein the p-type clad layer includes one or more p-type In1-xAlxP layers, the Al composition x of each of the one or more p-type In1-xAlxP layers is equal to or greater than a value corresponding to the doping concentration of a p-type dopant, and the absolute value of the average strain amount of the whole of the p-type clad layer is equal to or less than the absolute value of a critical strain amount obtained by Matthews' relational expression, using the entire layer thickness of the whole of the p-type clad layer as a critical layer thickness.

公开(公告)号：US09910220B2

公开(公告)日：2018-03-06

申请号：US14794106

申请日：2015-07-08

Applicant: The Regents of the University of California

Inventor： John E. Bowers

IPC: H01L31/18 ,  G02B6/122 ,  H01S5/02 ,  H01S5/026 ,  H01S5/125 ,  G02B6/12 ,  G02F1/017 ,  H01S5/343 ,  H01L27/146 ,  H01L31/12 ,  H01S5/183

CPC classification number: G02B6/1225 ,  G02B6/12002 ,  G02B2006/12061 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12128 ,  G02B2006/12147 ,  G02F1/01708 ,  H01L27/146 ,  H01L31/125 ,  H01L31/1852 ,  H01S5/0208 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/0217 ,  H01S5/0261 ,  H01S5/0268 ,  H01S5/125 ,  H01S5/18341 ,  H01S5/18369 ,  H01S5/343 ,  Y02E10/544 ,  Y02P70/521

Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of HI-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.

公开(公告)号：US09865994B2

公开(公告)日：2018-01-09

申请号：US15002607

申请日：2016-01-21

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Ippei Matsubara ,  Takayuki Kona ,  Keiji Iwata

IPC: H01S5/00 ,  H01S3/13 ,  H01S5/42 ,  H01S5/022 ,  H01S5/40 ,  H01S5/02 ,  H01S5/187 ,  H01S5/042 ,  H01S5/183

CPC classification number: H01S5/423 ,  H01L2224/24 ,  H01S5/0042 ,  H01S5/0208 ,  H01S5/02276 ,  H01S5/042 ,  H01S5/0425 ,  H01S5/18311 ,  H01S5/187 ,  H01S5/4018 ,  H01S2301/176

Abstract: A VCSEL array includes a base substrate, a plurality of VCSEL devices and an inter-device line. Each of the plurality of VCSEL devices is disposed on a front side of the base substrate. The inter-device line connects two of the plurality of VCSEL devices that are adjacent to each other, the two VCSEL devices being connected in series such that forward directions of the two VCSEL devices are the same. An insulating groove that electrically insulates the two VCSEL devices is formed on the base substrate.

公开(公告)号：US20170373471A1

公开(公告)日：2017-12-28

申请号：US15193069

申请日：2016-06-26

Applicant: VI Systems GmbH

Inventor： Joerg-Reinhardt KROPP ,  Nikolay LEDENTSOV ,  Vitaly SHCHUKIN

IPC: H01S5/22 ,  H01S5/187 ,  H01S5/183 ,  H01S5/042 ,  H01S5/30 ,  H01S5/02

CPC classification number: H01S5/18316 ,  H01L31/00 ,  H01L31/022408 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01S5/0208 ,  H01S5/0421 ,  H01S5/0425 ,  H01S5/06226 ,  H01S5/183 ,  H01S5/18308 ,  H01S5/18313 ,  H01S5/18327 ,  H01S5/1833 ,  H01S5/187 ,  H01S5/2202 ,  H01S5/2214 ,  H01S5/305 ,  H01S5/3054 ,  H01S5/32

Abstract: An optoelectronic semiconductor device is disclosed wherein the device is a vertical-cavity surface-emitting laser or a photodiode containing a section, the top part of which is electrically isolated from the rest of the device. The electric isolation can be realized by etching a set of holes and selective oxidation of AlGaAs layer or layers such that the oxide forms a continuous layer or layers everywhere beneath the top surface of this section. Alternatively, a device can be grown epitaxially on a semi-insulating substrate, and a round trench around a section of the device can be etched down to the semi-insulating substrate thus isolating this section electrically from the rest of the device. Then if top contact pads are deposited on top of the electrically isolated section, the pads have a low capacitance, and a pad capacitance below two hundred femto-Farads, and the total capacitance of the device below three hundred femto-Farads can be reached.

公开(公告)号：US20170194765A1

公开(公告)日：2017-07-06

申请号：US15338753

申请日：2016-10-31

Applicant: Northwestern University

Inventor： Manijeh Razeghi

IPC: H01S5/0687 ,  H01S5/34 ,  H01S5/12 ,  G01N21/39 ,  H01S5/343 ,  H01S5/028 ,  G01N21/3504 ,  H01S5/40 ,  H01S5/10

CPC classification number: H01S5/0687 ,  G01N21/3504 ,  G01N21/39 ,  G01N2021/3595 ,  G01N2021/399 ,  G02B6/00 ,  H01S5/0208 ,  H01S5/026 ,  H01S5/028 ,  H01S5/0287 ,  H01S5/06258 ,  H01S5/1028 ,  H01S5/1209 ,  H01S5/22 ,  H01S5/3401 ,  H01S5/34313 ,  H01S5/4012 ,  H01S5/4037 ,  H01S5/4087

Abstract: Monolithic, wavelength-tunable QCL devices are provided which comprise a substrate, an array of QCLs formed on the substrate and an optical beam combiner formed on the substrate electrically isolated from the array of QCLs. In embodiments, the QCL devices are configured to provide laser emission in the range of from about 3 μm to about 12 μm, a wavelength tuning range of at least about 500 cm−1, and a wavelength tuning step size of about 1.0 nm or less.

公开(公告)号：US09252079B2

公开(公告)日：2016-02-02

申请号：US14472391

申请日：2014-08-29

Applicant: Industrial Technology Research Institute

Inventor： Yao-Jun Tsai ,  Chen-Peng Hsu ,  Shih-Yi Wen ,  Chi-Chin Yang ,  Hung-Lieh Hu

IPC: H01L21/00 ,  H01L29/00 ,  H01L23/48 ,  H01L21/306 ,  H01L27/02 ,  H01L33/20 ,  H01L33/62 ,  H01L21/768 ,  H01L23/00 ,  H01S5/02 ,  H01S5/024 ,  H01S5/026 ,  H01S5/34 ,  G02B6/12 ,  G02B6/34 ,  H01L29/861 ,  H01L23/60 ,  H01L25/16

CPC classification number: H01L23/481 ,  G02B6/12 ,  G02B6/34 ,  G02B2006/12061 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L25/167 ,  H01L27/0255 ,  H01L29/861 ,  H01L33/20 ,  H01L33/62 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/08148 ,  H01L2224/08238 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/29294 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48148 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/80801 ,  H01L2224/80805 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83805 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2933/0066 ,  H01S5/0208 ,  H01S5/02469 ,  H01S5/026 ,  H01S5/34 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Provided is a substrate, including a substrate material, two conductive structures, and at least one diode. The two conductive structures extend from a first surface of the substrate material to a second surface of the substrate material via two through holes penetrating through the substrate material. The at least one diode is embedded in the substrate material at a sidewall of one of the through holes.

Abstract translation: 提供了包括基板材料，两个导电结构和至少一个二极管的基板。 两个导电结构通过穿过衬底材料的两个通孔从衬底材料的第一表面延伸到衬底材料的第二表面。 所述至少一个二极管被嵌入在所述通孔之一的侧壁处的所述衬底材料中。

公开(公告)号：US20150311675A1

公开(公告)日：2015-10-29

申请号：US14737103

申请日：2015-06-11

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Keiji IWATA ,  Ippei MATSUBARA ,  Takayuki KONA ,  Hiroshi WATANABE ,  Masashi YANAGASE

IPC: H01S5/183 ,  H01S5/343 ,  H01S5/042

CPC classification number: H01S5/18394 ,  H01S5/0208 ,  H01S5/0421 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/18311 ,  H01S5/18383 ,  H01S5/3432 ,  H01S2301/176

Abstract: Provided are a base substrate made of a semi-insulating semiconductor; an emission region multilayer unit formed on a surface of the base substrate and including each of an N-type semiconductor contact layer, an N-type DBR layer, an active layer, a P-type semiconductor DBR layer, and a P-type semiconductor contact layer; an anode electrode connected to the P-type semiconductor contact layer; and a cathode electrode formed on a surface side of the base substrate and connected to the N-type semiconductor contact layer. The N-type DBR layer is formed of 15 or more pairs of layers with different compositions laminated on each other. Through this configuration, a vertical-cavity surface-emitting laser that can suppress an occurrence of a defect caused by crystal missing arising from the base substrate can be provided at reduced cost.

Abstract translation: 提供由半绝缘半导体制成的基底基板; 形成在所述基底基板的表面上并且包括N型半导体接触层，N型DBR层，有源层，P型半导体DBR层和P型半导体中的每一个的发射区域多层单元 接触层; 连接到P型半导体接触层的阳极; 以及形成在所述基底基板的表面侧并与所述N型半导体接触层连接的阴极电极。 N型DBR层由具有不同组成的15层或更多层相互层叠而形成。 通过这种构造，可以以降低的成本提供能够抑制由基底基板引起的晶体缺陷引起的缺陷的发生的垂直腔表面发射激光器。

公开(公告)号：US20150309254A1

公开(公告)日：2015-10-29

申请号：US14794106

申请日：2015-07-08

Applicant: The Regents of the University of California

Inventor： John E. Bowers

IPC: G02B6/122 ,  H01S5/125 ,  H01S5/026 ,  G02B6/12 ,  H01S5/02

CPC classification number: G02B6/1225 ,  G02B6/12002 ,  G02B2006/12061 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12128 ,  G02B2006/12147 ,  G02F1/01708 ,  H01L27/146 ,  H01L31/125 ,  H01L31/1852 ,  H01S5/0208 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/0217 ,  H01S5/0261 ,  H01S5/0268 ,  H01S5/125 ,  H01S5/18341 ,  H01S5/18369 ,  H01S5/343 ,  Y02E10/544 ,  Y02P70/521

Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of HI-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.

Abstract translation: 公开了硅上的光子集成电路。 通过将作为有源区的HI-V材料的晶片结合到硅并去除衬底，可以使用硅衬底上的标准光刻技术来处理激光器，放大器，调制器和其它器件。 硅波导和III-V增益区之间的耦合允许集成低阈值激光器，可调谐激光器和其他具有免费金属氧化物半导体（CMOS）集成电路的光子集成电路。