公开(公告)号：US20230394348A1

公开(公告)日：2023-12-07

申请号：US18115091

申请日：2023-02-28

Applicant: Hitachi, Ltd.

Inventor： Satoru AKIYAMA ,  Takeru UTSUGI ,  Yusuke WACHI ,  Satoshi MURAOKA

IPC: G06N10/40 ,  H05K7/20 ,  H05K1/18 ,  H05K1/11

CPC classification number: G06N10/40 ,  H05K1/111 ,  H05K1/181 ,  H05K7/20272

Abstract: The invention addresses providing a technology that enables it to restrain a temperature rise because of current consumed by a quantum semiconductor and wiring conductors for control. A quantum calculator disclosed herein comprises a first refrigeration tube to cool a metal body; a refrigerator framing which encloses inside the metallic body and the first refrigeration tube; a quantum bit array chip having a plurality of silicon-spin quantum bits; and multiple control wiring conductors to drive the quantum bit array chip. The quantum bit array chip is placed on the metal body and made up of multiple regions and sub-regions, each of the regions performing a quantum operation independently. The multiple control wiring conductors are connected to the multiple regions and sub-regions respectively as multiple groups of control wiring conductors. The multiple control wring conductors are disposed across the first refrigeration tube.

公开(公告)号：US20220271213A1

公开(公告)日：2022-08-25

申请号：US17590965

申请日：2022-02-02

Applicant: Hitachi, Ltd

Inventor： Digh HISAMOTO ,  Satoru AKIYAMA ,  Toshiyuki MINE ,  Noriyuki LEE ,  Gou SHINKAI ,  Shinichi SAITO ,  Ryuta TSUCHIYA

IPC: H01L39/22 ,  H01L27/18 ,  H01L39/24 ,  G06N10/40

Abstract: A semiconductor device includes an active region famed in a semiconductor layer formed on an insulating film famed in a semiconductor substrate and having a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting with the first direction, a first diffusion layer electrode of a first conductivity type provided in the first extension portion, second and third diffusion layer electrodes of a second conductivity type provided in the second extension portion so as to interpose a first connecting portion connecting the first extension portion and the second extension portion, a first gate electrode famed on the first extension portion between the first diffusion layer electrode and the first connecting portion through an insulating film famed on the semiconductor layer, and a second gate electrode famed on the first connecting portion through the insulating film famed on the semiconductor layer.

公开(公告)号：US20160164413A1

公开(公告)日：2016-06-09

申请号：US14908867

申请日：2013-08-01

Applicant: HITACHI, LTD.

Inventor： Satoru AKIYAMA

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M7/537 ,  H02M2001/0009 ,  H03K5/131 ,  H03K17/04206 ,  H03K17/165 ,  H03K2217/0036 ,  H03K2217/0081

Abstract: Provided is a semiconductor device which drives a power semiconductor device, in which dead times generated when switch elements of upper and lower arms are turned on and off are minimized, and a loss of a power conversion device is reduced. A semiconductor device used in a power conversion device that includes a first switch element of which the drain is connected to a first power source voltage and a second switch element of which the source is connected to a second power source voltage includes a first drive circuit that drives the first switch element, a second drive circuit that drives the second switch element, a first level shift circuit, and a second level shift circuit. The first drive circuit is connected to a third power source voltage higher by a predetermined potential with respect to a source potential of the first switch element and the source potential of the first switch element. The second drive circuit is connected to a fourth power source voltage higher by a predetermined potential with respect to the second power source voltage and the second power source voltage. Power source potentials input to the first level shift circuit and the second level shift circuit are the third power source voltage and the second power source voltage.

Abstract translation: 提供了驱动功率半导体器件的半导体器件，其中上下臂的开关元件导通和关断时产生的死区时间最小化，并且功率转换器件的损耗降低。 一种电力转换装置中使用的半导体装置，其包括：第一开关元件，漏极与第一电源电压连接;第二开关元件，源极与第二电源电压连接，第一驱动电路， 驱动第一开关元件，驱动第二开关元件的第二驱动电路，第一电平移位电路和第二电平移位电路。 第一驱动电路相对于第一开关元件的源极电位和第一开关元件的源极电位被连接到高于预定电位的第三电源电压。 第二驱动电路相对于第二电源电压和第二电源电压被连接到比预定电位高的第四电源电压。 输入到第一电平移位电路和第二电平移位电路的电源电位是第三电源电压和第二电源电压。

公开(公告)号：US20150349115A1

公开(公告)日：2015-12-03

申请号：US14760166

申请日：2013-01-23

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Digh HISAMOTO ,  Satoru AKIYAMA ,  Takashi TAKAHAMA ,  Tadao MORIMOTO ,  Ryuta TSUCHIYA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/16 ,  H01L21/265

CPC classification number: H01L29/7813 ,  H01L21/02529 ,  H01L21/047 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Abstract translation: 这里公开了一种实现高性能和高可靠性的碳化硅半导体器件的技术。 具有通过p型体层105形成在漂移中的沟槽的沟槽MISFET包括覆盖沟槽底部的n型电阻缓和层109和p型场弛豫层108. p型场 松弛层108经由电阻缓和层109与沟槽底部分离，并且比电阻缓和层109宽。这样实现了低导通电阻，高可靠性和高耐压性。 通过在沟槽下方形成场弛豫层，可以控制反馈电容以实现高开关率和高可靠性。

公开(公告)号：US20180375509A1

公开(公告)日：2018-12-27

申请号：US15777126

申请日：2016-06-24

Applicant: HITACHI, LTD.

Inventor： Satoru AKIYAMA ,  Ryuusei FUJITA

IPC: H03K17/16 ,  H02M7/5387 ,  H02P27/06 ,  H02M1/08 ,  B61C3/00

CPC classification number: H03K17/162 ,  B61C3/00 ,  H02M1/08 ,  H02M7/5387 ,  H02P27/06 ,  H03K17/06 ,  H03K17/163 ,  H03K17/168 ,  H03K2017/066

Abstract: A gate drive circuit to prevent a false turn-on phenomenon includes a first, second, third and fourth switching element, and a capacitor. A source of the first switching element is connected to a first voltage, and a drain of the same is connected to the main switching element's gate electrode. A source of the second switching element is connected to a second voltage, and a drain of the same is connected to the gate electrode. A source of the third switching element is connected to the first voltage, and a drain of the same is connected to a first electrode of the capacitor. A source of the fourth switching element is connected to the second voltage, and a drain of the same is connected to the first electrode and to the drain of the third switching element. A second electrode of the capacitor is connected to the gate electrode.

公开(公告)号：US20230378759A1

公开(公告)日：2023-11-23

申请号：US18031361

申请日：2021-10-06

Applicant: HITACHI, LTD.

Inventor： Ryo WAKABAYASHI ,  Toru KOUNO ,  Satoru AKIYAMA ,  Emha Bayu MIFTAHULLATIF ,  Katsutoshi KONDO

IPC: H02J3/38 ,  H02J3/32

CPC classification number: H02J3/381 ,  H02J3/32 ,  H02J2300/24

Abstract: An object of the invention is to provide a control technique capable of connecting a storage battery to a DC bus via a DC/DC converter and controlling charging and discharging of the storage battery by the DC/DC converter. A DC grid system according to the invention calculates a voltage command value of a DC bus using a present voltage of a storage battery and a target voltage of the storage battery, and provides the voltage command value as a command value for each of an AC/DC converter and a DC/DC converter (see FIG. 1).

公开(公告)号：US20180026009A1

公开(公告)日：2018-01-25

申请号：US15527089

申请日：2015-03-13

Applicant: HITACHI, LTD.

Inventor： Ryuusei FUJITA ,  Satoru AKIYAMA ,  Hiroshi KAGEYAMA ,  Toru MASUDA ,  Ayumu HATANAKA ,  Akio SHIMA

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/467 ,  H02P27/06 ,  B60L11/18 ,  H02M7/00 ,  H01L27/06

CPC classification number: H01L25/0655 ,  B60L11/1803 ,  B60L11/1812 ,  B60L15/007 ,  H01L23/467 ,  H01L23/49844 ,  H01L25/00 ,  H01L27/0629 ,  H01L2224/0603 ,  H01L2224/49111 ,  H01L2224/49113 ,  H02M7/003 ,  H02P27/06

Abstract: The object of the present invention is to compensate for a difference in threshold voltage between a plurality of switching devices incorporated in a power module.The present invention solves the subject described above by mounting a switching device having a high threshold voltage in comparison with a different switching device at a location at which the temperature of the power module during operation is higher than that at another location at which the different switching device is mounted. Eventually, a power conversion apparatus of a high performance and a vehicle drive apparatus of a high performance can be provided.