公开(公告)号：US20150355846A1

公开(公告)日：2015-12-10

申请号：US14763019

申请日：2013-03-27

Applicant: HITACHI, LTD.

Inventor： Yutaka UEMATSU ,  Satoshi MURAOKA ,  Hideki OSAKA ,  Masabumi SHIBATA ,  Yuusuke FUKUMURA ,  Satoru WATANABE ,  Hiroshi KAKITA ,  Akio IDEI ,  Hitoshi UENO ,  Takayuki ONO ,  Takashi MIYAGAWA ,  Michinori NAITO ,  Taishi SUMIKURA ,  Yuichi FUKUDA

IPC: G06F3/06

CPC classification number: G06F3/068 ,  G06F3/0611 ,  G06F3/0629 ,  G06F13/1694 ,  G11C5/04 ,  G11C7/10

Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

Abstract translation: 作为速度较低但容量大于DRAM的高速存储器和闪速存储器的DRAM将被安装在DIMM上时，最大限度地提高CPU存储器总线吞吐量的重要性是安装组件的布置。 本公开提供了一种存储器模块（DIMM），其包括布置在更靠近插座端子的模块表面上的存储器控​​制器和用作布置在背面上的高速存储器的DRAM。 作为大容量存储器的非易失性存储器被布置在距离插座端子更远的一侧。

公开(公告)号：US20230394348A1

公开(公告)日：2023-12-07

申请号：US18115091

申请日：2023-02-28

Applicant: Hitachi, Ltd.

Inventor： Satoru AKIYAMA ,  Takeru UTSUGI ,  Yusuke WACHI ,  Satoshi MURAOKA

IPC: G06N10/40 ,  H05K7/20 ,  H05K1/18 ,  H05K1/11

CPC classification number: G06N10/40 ,  H05K1/111 ,  H05K1/181 ,  H05K7/20272

Abstract: The invention addresses providing a technology that enables it to restrain a temperature rise because of current consumed by a quantum semiconductor and wiring conductors for control. A quantum calculator disclosed herein comprises a first refrigeration tube to cool a metal body; a refrigerator framing which encloses inside the metallic body and the first refrigeration tube; a quantum bit array chip having a plurality of silicon-spin quantum bits; and multiple control wiring conductors to drive the quantum bit array chip. The quantum bit array chip is placed on the metal body and made up of multiple regions and sub-regions, each of the regions performing a quantum operation independently. The multiple control wiring conductors are connected to the multiple regions and sub-regions respectively as multiple groups of control wiring conductors. The multiple control wring conductors are disposed across the first refrigeration tube.

公开(公告)号：US20170220492A1

公开(公告)日：2017-08-03

申请号：US15114424

申请日：2014-05-16

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Satoshi MURAOKA

IPC: G06F13/16 ,  G11C29/10 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/102 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/42 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10 ,  G11C29/12005 ,  G11C29/24 ,  G11C29/50008 ,  G11C2029/1208 ,  G11C2029/5002 ,  G11C2029/5004 ,  G11C2029/5006 ,  G11C2207/2254 ,  H04L25/02 ,  H04L25/03

Abstract: A storage system includes a controller part, a data storage part, and a transfer path of a signal that couples these parts. A driver included in the controller part transmits the signal including write data on the basis of a configured parameter, a receiver included in the data storage part receives the signal, and the write data included in the signal is written into a first storage area. The controller part reads the write data from the first storage area, determines whether or not a bit error exists in the write data, changes the parameter when the bit error exists to repeat similar determination and find an appropriate parameter at which the bit error no longer exists.

公开(公告)号：US20160092351A1

公开(公告)日：2016-03-31

申请号：US14764838

申请日：2013-06-20

Applicant: HITACHI, LTD.

Inventor： Yutaka UEMATSU ,  Satoshi MURAOKA ,  Hiroshi KAKITA ,  Akio IDEI ,  Yusuke FUKUMURA ,  Satoru WATANABE ,  Takayuki ONO ,  Taishi SUMIKURA ,  Yuichi FUKUDA ,  Takashi MIYAGAWA ,  Michinori NAITO ,  Hideki OSAKA ,  Masabumi SHIBATA ,  Hitoshi UENO ,  Kazunori NAKAJIMA ,  Yoshihiro KONDO

IPC: G06F12/02 ,  G11C16/04 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F12/0638 ,  G06F2212/2532 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C16/0491

Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Abstract translation: 具有安装在双面基板上的不同类型存储器的存储器模块具有第一边缘和相对的第二边缘，并且包括多个存储器控制器，多个闪速存储器和具有较高信号传输速率的多个第二存储器 比闪存。 在第一边缘侧的双面基板的前表面和后表面上形成用于将双面基板连接到主板的插座端子; 存储器控制器设置在第二边缘侧; 第二存储器在与存储器控制器的位置相反的位置处设置在第二边缘侧; 并且在存储器控制器和第二存储器的位置比位于比第一边缘更靠近的位置处，至少在其后表面上布置闪速存储器。

公开(公告)号：US20150347032A1

公开(公告)日：2015-12-03

申请号：US14759504

申请日：2013-03-27

Applicant: HITACHI, LTD.

Inventor： Satoshi MURAOKA ,  Yutaka UEMATSU ,  Hideki OSAKA ,  Yuusuke FUKUMURA ,  Satoru WATANABE ,  Masabumi SHIBATA ,  Hiroshi KAKITA ,  Yuichi FUKUDA ,  Takashi MIYAGAWA ,  Michinori NAITO ,  Hitoshi UENO ,  Akio IDEI ,  Takayuki ONO ,  Taishi SUMIKURA

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1694 ,  G11C5/04 ,  G11C7/10

Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

Abstract translation: 在将由DRAM构成的存储器模块（即高速存储器）和由比DRAM慢的高容量存储器的闪速存储器构成的存储器模块连接到CPU存储器总线的方法中，在顺序读取的情况下， CPU内存总线的繁忙速度增加，容易发生性能下降。 在本发明中，信息处理装置具有CPU，CPU存储器总线和主存储装置。 主存储装置具有第一存储器模块和第二存储器模块。 第一个内存模块具有高速内存。 第二存储器模块具有与高速存储器相同的存储器接口的存储器，具有与高速存储器的存储器接口不同的存储器接口的高容量存储器，以及控制器。 使第一存储器模块和第二存储器模块被高速存储器的存储器接口访问。