摘要:
A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
摘要:
In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.
摘要:
A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.
摘要:
A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.
摘要:
A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.
摘要:
The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.
摘要:
A semiconductor memory device having a structure in which a data input/output line is shared by a plurality of banks is provided. In the semiconductor memory device which has a memory block including a plurality of banks, data of a selected memory cell is input or output via a data input/output line. When data is written to a memory cell, the memory block is divided into at least two bank groups and the data input/output line is divided into at least two data input/output lines to separately connect the data input/output line to the respective bank groups so that the data is written to the selected memory cell via the data input/output line connected to a bank group including the selected memory cell. When data of a selected memory cell is read, the local data input/output lines are connected. Therefore, reduction of speed and power consumption is minimized and loads of data input/output lines are regulated during the read and write operations.