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    Method for forming capacitor of semiconductor device using pre-bake
    2.
    发明授权
    Method for forming capacitor of semiconductor device using pre-bake 失效
    使用预烘烤形成半导体器件的电容器的方法

    公开(公告)号：US6146935A

    公开(公告)日：2000-11-14

    申请号：US148172

    申请日：1998-09-04

    申请人： Hong-bae Park ,  Cha-Young Yoo

    发明人： Hong-bae Park ,  Cha-Young Yoo

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/314 ,  H01L21/822 ,  H01L27/02 ,  H01L21/8242 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L28/55

    摘要： A method for forming a capacitor of a semiconductor device. A lower electrode is prebaked before a dielectric layer is formed on the lower electrode. As a result, moisture or contaminants are removed from the lower electrode, increasing adhesion between the lower electrode and the dielectric layer formed on the lower electrode, thereby preventing the dielectric layer from being lifted and cracked due to inferior coating properties.

    摘要翻译： 一种形成半导体器件的电容器的方法。 在下电极上形成电介质层之前，对下电极进行预烘烤。 结果，从下部电极去除了水分或污染物，增加了下部电极和形成在下部电极上的电介质层之间的粘附性，从而防止了介电层由于劣化的涂层性能而被提升和破裂。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE
    4.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE 审中-公开
    制造具有双门的半导体器件的方法

    公开(公告)号：US20110223758A1

    公开(公告)日：2011-09-15

    申请号：US13116045

    申请日：2011-05-26

    申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

    摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

    摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

    Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the same
    5.
    发明授权
    Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the same 有权
    具有金属栅叠层结构的互补金属氧化物半导体器件及其制造方法

    公开(公告)号：US08513740B2

    公开(公告)日：2013-08-20

    申请号：US12873611

    申请日：2010-09-01

    申请人： Hong-bae Park ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-ju Na ,  Hye-lan Lee ,  Hyung-seok Hong

    发明人： Hong-bae Park ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-ju Na ,  Hye-lan Lee ,  Hyung-seok Hong

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    摘要： A complementary metal oxide semiconductor (CMOS) device including: a semiconductor substrate including a NMOS region and a PMOS region; a NMOS metal gate stack structure on the NMOS region and including a first high dielectric layer, a first barrier metal gate on the first high dielectric layer and including a metal oxide nitride layer, and a first metal gate on the first barrier metal gate; and a PMOS metal gate stack structure on the PMOS region and including a second high dielectric layer, a second barrier metal gate on the second high dielectric layer and including a metal oxide nitride layer, and a second metal gate on the second barrier metal gate.

    摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括：包括NMOS区域和PMOS区域的半导体衬底; 在NMOS区域上的NMOS金属栅叠层结构，包括第一高介电层，第一高电介质层上的第一势垒金属栅极，并且包括金属氧化物氮化物层，以及第一栅极金属栅极上的第一金属栅极; 以及在PMOS区域上的PMOS金属栅极堆叠结构，并且包括第二高介电层，第二高介电层上的第二阻挡金属栅极，并且包括金属氧化物氮化物层，以及在第二阻挡金属栅极上的第二金属栅极。

    High dielectric film and related method of manufacture
    6.
    发明授权
    High dielectric film and related method of manufacture 有权
    高介电膜及相关制造方法

    公开(公告)号：US07521331B2

    公开(公告)日：2009-04-21

    申请号：US11359404

    申请日：2006-02-23

    申请人： Hong-bae Park ,  Yu-gyun Shin ,  Sang-bom Kang

    发明人： Hong-bae Park ,  Yu-gyun Shin ,  Sang-bom Kang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  H01L21/02142 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31645

    摘要： A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time interval, supplying a second source gas to the reaction chamber for a third time interval after the second time interval, supplying a second reactant gas to the reaction chamber for a fourth time interval after the third time interval, and supplying an additive gas including nitrogen to the reaction chamber during a fifth time interval.

    摘要翻译： 形成用于半导体器件的高电介质膜的方法包括：在第一时间间隔内将第一源气体供应到反应室，在第一时间间隔之后的第二时间间隔期间将第一反应气体供应到反应室， 在所述第二时间间隔之后的第三时间间隔内将第二源气体供应到所述反应室，在所述第三时间间隔之后，将第二反应气体供应到所述反应室中第四时间间隔，并且在所述第三时间间隔内向所述反应室供应包含氮气的添加剂气体 第五个时间间隔。

    Method of manufacturing dual gate semiconductor device
    7.
    发明授权
    Method of manufacturing dual gate semiconductor device 有权
    双栅极半导体器件的制造方法

    公开(公告)号：US08367502B2

    公开(公告)日：2013-02-05

    申请号：US12654337

    申请日：2009-12-17

    申请人： Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-joo Nah ,  Hyung-seok Hong

    发明人： Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-joo Nah ,  Hyung-seok Hong

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/82385

    摘要： The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities.

    摘要翻译： 该方法包括提供包括将要形成不同的导电金属氧化物半导体（MOS）晶体管的第一和第二区域的半导体衬底。 在所述半导体衬底上方的栅极电介质层，其顺序地在所述栅极电介质层上方形成第一金属导电层和第二金属导电层; 用掩模覆盖第二区域，并且将第一材料离子种植到第一区域的第一金属导电层中。 通过图案化第一区域的栅介电层和第一金属导电层，去除第一区域的第二金属导电层并形成第一区域的第一栅极电极和第二区域的第二栅极电极，以及栅极电介质 第一金属导电层和第二区域的第二金属导电层。 由于第一和第二区域的栅电极具有不同的厚度，并且第一和第二栅电极中的至少一个包括杂质，所以具有不同功函数的半导体衬底的第一和第二区域。

    Ferroelectric random access memory device and fabrication method therefor
    9.
    发明授权
    Ferroelectric random access memory device and fabrication method therefor 失效
    铁电随机存取存储器件及其制造方法

    公开(公告)号：US06929956B2

    公开(公告)日：2005-08-16

    申请号：US09800904

    申请日：2001-03-08

    申请人： Byung-hee Kim ,  Hong-bae Park

    发明人： Byung-hee Kim ,  Hong-bae Park

    IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/336 ,  H01L21/3105

    CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02356 ,  H01L21/02362 ,  H01L27/11507 ,  H01L28/56

    摘要： A ferroelectric random access memory (FRAM) device, and a fabrication method therefor, includes seed layers above and below a ferroelectric layer. The seed layers formed above and below faces of the ferroelectric layer can prevent an imprint phenomenon from being generated in a ferroelectric capacitor by making the characteristics of the upper and lower interfaces of the ferroelectric layer be the same. This is accomplished by providing upper and lower seed layers that are crystallized prior to the ferroelectric layer during a thermal treatment. This results in crystallization occurring from the upper and lower faces to the center of the ferroelectric layer, making the characteristics of the upper and lower interfaces of the ferroelectric layer the same, thereby improving ferroelectric capacitor characteristics.

    摘要翻译： 铁电随机存取存储器（FRAM）及其制造方法包括铁电层上方和下方的种子层。 形成在铁电体层的上下面的种子层可以防止铁电体电容器中的上下界面的特性相同而产生印制现象。 这是通过在热处理期间提供在铁电层之前结晶的上和下种子层来实现的。 这导致从铁电层的上下面到中心发生结晶，使铁电层的上下界面的特性相同，从而提高铁电电容器的特性。

    Method of fabricating semiconductor device having dual gate
    10.
    发明授权
    Method of fabricating semiconductor device having dual gate 有权
    制造具有双栅极的半导体器件的方法

    公开(公告)号：US07972950B2

    公开(公告)日：2011-07-05

    申请号：US12580302

    申请日：2009-10-16

    申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

    摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

    摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。