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    Method for forming a fully germano-silicided gate MOSFET and devices obtained thereof
    3.
    发明申请
    Method for forming a fully germano-silicided gate MOSFET and devices obtained thereof 审中-公开
    用于形成完全锗硅化物栅极MOSFET的方法及其获得的器件

    公开(公告)号：US20070023849A1

    公开(公告)日：2007-02-01

    申请号：US11484438

    申请日：2006-07-11

    申请人： HongYu Yu ,  Serge Biesemans

    发明人： HongYu Yu ,  Serge Biesemans

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/785

    摘要： A MOSFET comprising a fully germano-silicided gate electrode having a high work function is disclosed. This gate electrode is formed by a self-aligned reaction process between a silicidation metal and a semiconductor material comprising silicon and germanium. Preferably, the fully germano-silicided gate is formed by a reaction between nickel and SiGe. The work function of the fully germano-silicided gate electrode can be tuned.

    摘要翻译： 公开了一种包括具有高功函数的完全锗硅化栅电极的MOSFET。 该栅极通过硅化金属与包含硅和锗的半导体材料之间的自对准反应工艺形成。 优选地，通过镍和SiGe之间的反应形成完全锗硅化的栅极。 可以调整完全锗硅化物栅电极的功能。

    Method for forming an electronic device
    4.
    发明授权
    Method for forming an electronic device 失效
    电子设备的形成方法

    公开(公告)号：US06884672B1

    公开(公告)日：2005-04-26

    申请号：US10701191

    申请日：2003-11-04

    申请人： Karanam Balasubramanyam ,  Serge Biesemans ,  Byeongju Park

    发明人： Karanam Balasubramanyam ,  Serge Biesemans ,  Byeongju Park

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49

    CPC分类号： H01L29/6656 ,  H01L21/28035 ,  H01L29/4925

    摘要： Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.

    摘要翻译： 在本发明的范围内，在栅绝缘层上形成非晶硅层。 在非晶硅层上形成栅极电介质。 然后将非晶硅层限制在至少一个在低温工艺下沉积的间隔物。 一旦至少一个间隔物就位，则非晶硅暴露于足够高的温度以将非晶硅转化为多晶硅。 通过等待直到非晶硅在将其转换成多晶硅之前被限制在至少一个间隔物内，则栅极长度的变化减小。

    Methods for manufacturing a CMOS device with dual dielectric layers
    5.
    发明申请
    Methods for manufacturing a CMOS device with dual dielectric layers 审中-公开
    制造具有双电介质层的CMOS器件的方法

    公开(公告)号：US20080191286A1

    公开(公告)日：2008-08-14

    申请号：US11972601

    申请日：2008-01-10

    申请人： Shou-Zen Chang ,  Hong Yu Yu ,  Anabela Veloso ,  Rita Vos ,  Stefan Kubicek ,  Serge Biesemans ,  Raghunath Singanamalla ,  Anne Lauwers ,  Bart Onsia

    发明人： Shou-Zen Chang ,  Hong Yu Yu ,  Anabela Veloso ,  Rita Vos ,  Stefan Kubicek ,  Serge Biesemans ,  Raghunath Singanamalla ,  Anne Lauwers ,  Bart Onsia

    IPC分类号： H01L27/00 ,  H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L29/785

    摘要： The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region. The method further includes changing the workfunction of the device on the first region by providing a capping layer onto the first region between the dielectric layer and the gate electrode, and changing the workfunction of the device on the second region by including species at the interface between the dielectric layer and the electrode.

    摘要翻译： 本公开提供了一种双功能半导体器件和用于制造双功能半导体器件的方法。 该方法包括在第一区域上提供器件和在衬底的第二区域上提供器件。 根据本文所述的实施例，该方法包括在基板的第一和第二区域上提供介电层，第一区域上的电介质层与第二区域上的电介质层整体沉积，并且在 所述第一区域和所述第二区域上的所述电介质层，所述第一区域上的所述栅电极与所述第二区域上的所述栅极电极整体地沉积。 该方法还包括通过在介电层和栅电极之间的第一区域上设置覆盖层来改变第一区域上的器件的功函数，以及通过在第二区域上的界面处包括物质来改变第二区域上的器件的功函数 介电层和电极。

    METHOD FOR FORMING AN ELECTRONIC DEVICE
    8.
    发明申请
    METHOD FOR FORMING AN ELECTRONIC DEVICE 失效
    形成电子设备的方法

    公开(公告)号：US20050095831A1

    公开(公告)日：2005-05-05

    申请号：US10701191

    申请日：2003-11-04

    申请人： Karanam Balasubramanyam ,  Serge Biesemans ,  Byeongju Park

    发明人： Karanam Balasubramanyam ,  Serge Biesemans ,  Byeongju Park

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49

    CPC分类号： H01L29/6656 ,  H01L21/28035 ,  H01L29/4925

    摘要： Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced

    摘要翻译： 在本发明的范围内，在栅绝缘层上形成非晶硅层。 在非晶硅层上形成栅极电介质。 然后将非晶硅层限制在至少一个在低温工艺下沉积的间隔物。 一旦至少一个间隔物就位，则非晶硅暴露于足够高的温度以将非晶硅转化为多晶硅。 通过等待直到非晶硅在将其转换成多晶硅之前被限制在至少一个间隔物内，则栅极长度的变化减小