公开(公告)号：US5057186A

公开(公告)日：1991-10-15

申请号：US597295

申请日：1990-10-12

申请人： Hongzong Chew ,  Catherine A. Fieber ,  Graham W. Hills ,  Edward P. Martin, Jr.

发明人： Hongzong Chew ,  Catherine A. Fieber ,  Graham W. Hills ,  Edward P. Martin, Jr.

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31138 ,  H01L21/76804

摘要： In a two-step etching process for making tapered contact openings in a dieletric, a thin layer of a material is interposed to serve as an adhesive between the dielectric and a photoresist layer the thin layer of material is chosen to remain essentially intact during undercut partial etching of the dielectric. As a result of enhanced adhesion, the photoresist layer remains more accurately positioned for subsequent anisotropic etching across the remainder of the thickness of the dielectric.

摘要翻译： 在用于在渐变的锥形接触开口中进行两步蚀刻工艺中，介入材料的薄层以用作电介质和光致抗蚀剂层之间的粘合剂，薄层材料被选择为在底切部分 蚀刻电介质。 由于附着力增强，光致抗蚀剂层保持更准确地定位，以便在电介质厚度的其余部分进行随后的各向异性蚀刻。

公开(公告)号：US5534108A

公开(公告)日：1996-07-09

申请号：US400468

申请日：1995-03-07

申请人： Xue-Yu Qian ,  Gerald Yin ,  Graham W. Hills ,  Robert Steger

发明人： Xue-Yu Qian ,  Gerald Yin ,  Graham W. Hills ,  Robert Steger

IPC分类号： H01J37/32 ,  H05H1/46 ,  H05H1/00

CPC分类号： H01J37/32623 ,  H01J37/3266 ,  H05H1/46

摘要： A magnetic field enhanced plasma etch reactor system and method of operation is disclosed. In the system and operation, modulated sinusoidal currents are generated and applied 90.degree. out of phase to opposing pairs of series connected electromagnets to produce a modified rotating magnetic field parallel to a substrate processed in the system. The modification of the rotating magnetic field, in turn, results in an improvement in the uniformity of the etch pattern over the upper surface of the substrate.

摘要翻译： 公开了一种磁场增强等离子体蚀刻反应器系统和操作方法。 在系统和操作中，产生调制的正弦电流并与相对的串联电磁体对相差90°，产生与系统中处理的衬底平行的改进的旋转磁场。 反过来，旋转磁场的改变导致蚀刻图案在衬底的上表面上的均匀性的改善。

公开(公告)号：US5744049A

公开(公告)日：1998-04-28

申请号：US276750

申请日：1994-07-18

申请人： Graham W. Hills ,  Yuh-Jia Su

发明人： Graham W. Hills ,  Yuh-Jia Su

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/02

CPC分类号： H01J37/32449 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32532 ,  H01J37/32642 ,  H01L21/3065 ,  Y10S156/915 ,  Y10S438/941

摘要： The invention improves etch uniformity across a silicon wafer surface in an RF plasma etch reactor. In a first aspect of the invention, etch uniformity is enhanced by reducing the etchant species (e.g., Chlorine) ion and radical densities near the wafer edge periphery without a concomitant reduction over the wafer center, by diluting the etchant (Chlorine) with a diluent gas which practically does not etch Silicon (e.g., Hydrogen Bromide) near the wafer edge periphery. In a second aspect of the invention, etch rate uniformity is enhanced by more rapidly disassociating Chlorine molecules over the center of the wafer to increase the local etch rate, without a concomitant hastening of Chlorine dissociation near the wafer periphery, by the introduction of an inert gas over the wafer center. In a third aspect of the invention, etch rate uniformity is enhanced by forcing gas flow from the gas distribution plate downward toward the wafer center to provide a greater concentration of Chlorine ions over the wafer center, by reducing the effective diameter of the chamber between the gas distribution plate and the wafer to approximately the diameter of the wafer. In a fourth aspect of the invention, etch rate uniformity is enhanced by reducing RF power near the wafer edge periphery, by reducing the RF pedestal to a diameter substantially less than that of the wafer.

摘要翻译： 本发明改进了RF等离子体蚀刻反应器中硅晶片表面的蚀刻均匀性。 在本发明的第一方面，通过在晶片边缘周围附近减少蚀刻剂物质（例如氯）离子和自由基密度而不会伴随晶片中心的减少，通过用稀释剂稀释蚀刻剂（氯）来增强蚀刻均匀性 实际上不会在晶片边缘周边附近蚀刻硅（例如，溴化氢）的气体。 在本发明的第二方面，通过在晶片中心更快速地分离氯分子来提高蚀刻速率均匀性，以增加局部蚀刻速率，而不会伴随着晶片周边附近的氯离解加速，通过引入惰性 气体在晶圆中心。 在本发明的第三方面中，通过迫使气体从气体分配板向下流向晶片中心来提高蚀刻速率的均匀性，以通过减小在晶片中心之间的腔的有效直径，从而在晶片中心上提供更大浓度的氯离子 气体分配板和晶片大约直到晶片的直径。 在本发明的第四方面，通过将RF基座减小至基本上小于晶片直径的直径，通过减小晶片边缘周边附近的RF功率来增强蚀刻速率均匀性。

公开(公告)号：US5685914A

公开(公告)日：1997-11-11

申请号：US223335

申请日：1994-04-05

申请人： Graham W. Hills ,  Yuh-Jia Su ,  Yoshiaki Tanase ,  Robert E. Ryan

发明人： Graham W. Hills ,  Yuh-Jia Su ,  Yoshiaki Tanase ,  Robert E. Ryan

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23F4/00 ,  H01J37/32 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  C23C16/00

CPC分类号： H01J37/32449 ,  H01J37/32642 ,  H01J2237/022 ,  Y10S156/915 ,  Y10S156/916

摘要： In one aspect, the invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a pedestal focus ring surrounding the periphery of the wafer for reducing the process etch rate near the wafer periphery, and plural openings through the pedestal focus ring which permit passage therethrough of particulate contamination, thereby reducing accumulation of particulate contamination near the wafer periphery. In another aspect, in order to reduce corrosive wear of the chamber walls, a removable gas distribution focus ring shields the side walls of the plasma reactor from reactive gases associated with processing of the semiconductor wafer.

摘要翻译： 在一个方面，本发明体现在用于处理半导体晶片的等离子体反应器中，反应器具有围绕晶片周边的基座聚焦环，用于降低晶片周边附近的工艺蚀刻速率，以及穿过基座聚焦环的多个开口 其允许颗粒污染通过，从而减少晶片周边附近的颗粒污染物的积聚。 在另一方面，为了减少室壁的腐蚀磨损，可移除的气体分配聚焦环屏蔽等离子体反应器的侧壁与与半导体晶片的处理有关的反应性气体。

公开(公告)号：US4980301A

公开(公告)日：1990-12-25

申请号：US485804

申请日：1990-02-23

申请人： Alain S. Harrus ,  Graham W. Hills ,  Cris W. Lawrence ,  Morgan J. Thoma

发明人： Alain S. Harrus ,  Graham W. Hills ,  Cris W. Lawrence ,  Morgan J. Thoma

IPC分类号： H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/3105 ,  H01L21/31111

摘要： In a method of fabricating semiconductor integrated circuits, the effects of mobile ion contamination in a dielectric layer which has been subjected to a source of mobile ion contamination, e.g., reactive ion etching, is substantially eliminated by removing substantially only the topmost portion of the dielectric layer, e.g., 10-15 nm of an 800 nm layer, promptly after performing the step which produced the source of contamination.

摘要翻译： 在制造半导体集成电路的方法中，通过仅仅去除电介质的最上部分，基本上消除了已经受到移动离子污染源（例如反应离子蚀刻）的电介质层中的移动离子污染的影响 层，例如800nm层的10-15nm，在执行产生污染源的步骤之后立即。

公开(公告)号：US5382316A

公开(公告)日：1995-01-17

申请号：US145357

申请日：1993-10-29

申请人： Graham W. Hills ,  Ruth E. Bucknall

发明人： Graham W. Hills ,  Ruth E. Bucknall

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/02071 ,  H01L21/31138

摘要： A plasma etch process is described for simultaneously removing photoresist and etch residues, such as silicon oxide residues, remaining on a substrate from a prior polysilicon and/or polycide etch. The process comprises: (a) generating radicals in a plasma generator upstream of an etch chamber, from an etch gas mixture comprising (i) oxygen, water vapor, or a mixture of same; and (ii) one or more fluorine-containing etchant gases; and (b) then contacting the substrate containing the photoresist and residues from the previous polysilicon/polycide etch with the generated radicals in the etch chamber to remove both the photoresist and the etch residues during the same etch step.

摘要翻译： 描述了等离子体蚀刻工艺，用于同时从先前的多晶硅和/或多晶硅蚀刻去除残留在衬底上的光致抗蚀剂和蚀刻残留物，例如氧化硅残余物。 该方法包括：（a）从蚀刻气体混合物在蚀刻室上游产生自由基，所述蚀刻气体混合物包括（i）氧，水蒸气或其混合物; 和（ii）一种或多种含氟蚀刻剂气体; 和（b）然后使包含光致抗蚀剂的基板和来自先前的多晶硅/多晶硅蚀刻的残余物与蚀刻室中产生的自由基接触，以在相同的蚀刻步骤期间去除光致抗蚀剂和蚀刻残留物。

公开(公告)号：US5242538A

公开(公告)日：1993-09-07

申请号：US827377

申请日：1992-01-29

申请人： Matt M. Hamrah ,  Graham W. Hills ,  Ian J. Morey

发明人： Matt M. Hamrah ,  Graham W. Hills ,  Ian J. Morey

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01J37/32082 ,  H01J37/3266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137

摘要： The addition of a gaseous source of hydrogen radicals, such as hydrogen, ammonia or methane to oxide RIE etching chemistries, in amounts of from about 5 to about 20 percent by volume of the total gas flow, will increase the oxide etch rate while suppressing the polysilicon etch rate. This effect is more pronounced at lower wafer temperatures. This new process chemistry increases the oxide etch rate to greater than 5000 .ANG./min., improves the selectivity to polysilicon to greater than 25:1 and improves the selectivity to photoresist to greater than 6:1, without having a significant detrimental effect on the profile angle, the RIE lag and the etch rate uniformity. Selectivities of 50:1 have been achieved with less than 15% RIE lag using the chemistry CHF.sub.3, Ar, CF.sub.4 and NH.sub.3, with NH.sub.3 constituting 10 percent by volume of the gas flow.

公开(公告)号：US6125788A

公开(公告)日：2000-10-03

申请号：US989282

申请日：1997-12-12

申请人： Graham W. Hills ,  Yuh-Jia Su

发明人： Graham W. Hills ,  Yuh-Jia Su

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  C23C16/00

CPC分类号： H01J37/32449 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32532 ,  H01J37/32642 ,  H01L21/3065 ,  Y10S156/915 ,  Y10S438/941

摘要： The invention improves etch uniformity across a silcon wafer surface in an RF plasma etch reactor. In a first aspect of the invention, etch uniformity is enhanced by reducing the etchant species (e.g., Chlorine) ion and radical densities near the wafer edge periphery without a concomitant reduction over the wafer center, by diluting the etchant (Chlorine) with a diluent gas which practically does not etch Silicon (e.g., Hydrogen Bromide) near the wafer edge periphery. In a second aspect of the invention, etch rate uniformity is enhanced by more rapidly disassociating Chlorine molecules over the center of the wafer to increase the local etch rate, without a concomitant hastening of Chlorine dissociation near the wafer periphery, by the introduction of an inert gas over the wafer center. In a third aspect of the invention, etch rate uniformity is enhanced by forcing gas flow from the gas distribution plate downward toward the wafer center to provide a greater concentration of Chlorine ions over the wafer center, by reducing the effective diameter of the chamber between the gas distribution plate and the wafer to approximately the diameter of the wafer. In a fourth aspect of the invention, etch rate uniformity is enhanced by reducing RF power near the wafer edge periphery, by reducing the RF pedestal to a diameter substantially less than that of the wafer.

摘要翻译： 本发明提高了RF等离子体蚀刻反应器中硅衬底晶片表面的蚀刻均匀性。 在本发明的第一方面，通过在晶片边缘周围附近减少蚀刻剂物质（例如氯）离子和自由基密度而不会伴随晶片中心的减少，通过用稀释剂稀释蚀刻剂（氯）来增强蚀刻均匀性 实际上不会在晶片边缘周边附近蚀刻硅（例如，溴化氢）的气体。 在本发明的第二方面，通过在晶片中心更快速地分离氯分子来提高蚀刻速率均匀性，以增加局部蚀刻速率，而不会伴随着晶片周边附近的氯离解加速，通过引入惰性 气体在晶圆中心。 在本发明的第三方面中，通过迫使气体从气体分配板向下流向晶片中心来提高蚀刻速率的均匀性，以通过减小在晶片中心之间的腔的有效直径，从而在晶片中心上提供更大浓度的氯离子 气体分配板和晶片大约直到晶片的直径。 在本发明的第四方面，通过将RF基座减小至基本上小于晶片直径的直径，通过减小晶片边缘周边附近的RF功率来增强蚀刻速率均匀性。

公开(公告)号：US5410122A

公开(公告)日：1995-04-25

申请号：US31800

申请日：1993-03-15

申请人： Yuh-Jia Su ,  Anand Gupta ,  Graham W. Hills ,  Joseph Lanucha

发明人： Yuh-Jia Su ,  Anand Gupta ,  Graham W. Hills ,  Joseph Lanucha

IPC分类号： H01J37/32 ,  B23K10/00 ,  B44C1/22 ,  H01L21/00

CPC分类号： H01J37/32431 ,  H01J2237/022

摘要： Particles are repelled from the upper face of a wafer in a plasma chamber by inducing positive or negative charges on the substrate without generating a gas plasma above the substrate. The charges are induced in the substrate by bringing a conductive sheet carrying a DC voltage close to the underside of the substrate. The particle repelling effect may be enhanced by inducing alternating positive and negative charges in the substrate. This can be done by switching the polarity of the DC voltage applied to the conductive sheet, or alternatively by moving an actuator to repetitively ground and isolate the substrate from the chamber.

摘要翻译： 通过在衬底上引起正电荷或负电荷而不在衬底上产生气体等离子体，在等离子体室中从晶片的上表面排出颗粒。 通过使承载DC电压的导电片靠近衬底的下侧而在衬底中感应电荷。 可以通过在衬底中诱导交替的正电荷和负电荷来增强颗粒排斥效应。 这可以通过切换施加到导电片的DC电压的极性，或者通过移动致动器来重复地接地并将衬底与腔室隔离来实现。

公开(公告)号：US5026666A

公开(公告)日：1991-06-25

申请号：US458114

申请日：1989-12-28

申请人： Graham W. Hills ,  Robert D. Huttemann ,  Kolawole R. Olasupo

发明人： Graham W. Hills ,  Robert D. Huttemann ,  Kolawole R. Olasupo

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/311 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L21/76819 ,  H01L21/31116 ,  H01L21/76802 ,  Y10S438/959

摘要： An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.