公开(公告)号：US5270243A

公开(公告)日：1993-12-14

申请号：US35232

申请日：1993-03-22

Applicant: Hsiao-Chin Tuan ,  Yih-Fang Liu

Inventor： Hsiao-Chin Tuan ,  Yih-Fang Liu

IPC: H01L21/8242 ,  H01L21/70

CPC classification number: H01L27/10852

Abstract: A method and resulting structure for defining a dielectric layer thickness and etching openings having a desired aspect ratio through said dielectric layer covering regions in the peripheral circuits of a DRAM integrated circuit to be electrically contacted in a semiconductor wafer is described. The DRAM integrated circuit including the peripheral circuits to be electrically contacted is provide in the semiconductor wafer. A first conductive polysilicon layer is formed over said DRAM integrated circuit and the layer is patterned to leave the layer over the peripheral circuits. A first interlevel dielectric layer is formed over the polysilicon layer which has been patterned. A second conductive polysilicon layer is formed over the first interlevel dielectric layer and patterned to leave the layer over areas other than the peripheral circuits. The first interlevel dielectric layer and first polysilicon layer thereunder are masked and etched to remove the first interlevel dielectric layer and first polysilicon layer from all the peripheral circuits. A second interlevel dielectric layer is formed over the exposed second conductive polysilicon layer, first interlevel dielectric and semiconductor wafer. The openings having a desired aspect ratio are etched through said second interlevel dielectric layer.

Abstract translation: 描述了一种用于限定介电层厚度的方法和结果，并且通过在半导体晶片中电接触的DRAM集成电路的外围电路中的所述介电层覆盖区域蚀刻具有期望的纵横比的开口。 在半导体晶片中提供包括要电接触的外围电路的DRAM集成电路。 在所述DRAM集成电路上形成第一导电多晶硅层，并且对该层进行图案化以将层留在外围电路上。 在图案化的多晶硅层上形成第一层间电介质层。 第二导电多晶硅层形成在第一层间电介质层之上，并被图案化以将层留在外围电路以外的区域上。 对其之下的第一层间介质层和第一多晶硅层进行掩模蚀刻以从所有外围电路去除第一层间介质层和第一多晶硅层。 在暴露的第二导电多晶硅层，第一层间介质和半导体晶片之上形成第二层间电介质层。 通过所述第二层间介质层蚀刻具有期望的纵横比的开口。

公开(公告)号：US08633086B2

公开(公告)日：2014-01-21

申请号：US12651322

申请日：2009-12-31

Applicant: Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

Inventor： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

IPC: H01L21/30

CPC classification number: H01L29/66712 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.

Abstract translation: 提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。 在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。 将晶片减薄至预定厚度。 多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。 然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。

公开(公告)号：US20130134512A1

公开(公告)日：2013-05-30

申请号：US13348463

申请日：2012-01-11

Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66659

Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate

Abstract translation: 功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。 栅极电介质和栅电极设置在半导体区域上。 与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。 电介质层具有在漂移区的顶表面上方并与其接触的部分。 导电场板在电介质层的上方。 源极区域和漏极区域在栅电极的相对侧上。 漏极区域与第一漂移区域接触。 底部金属层在场板上

公开(公告)号：US20110220995A1

公开(公告)日：2011-09-15

申请号：US12721045

申请日：2010-03-10

Applicant: Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

Inventor： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/42368 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

Abstract translation: 提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。 该器件包括形成在半导体衬底上的半导体衬底和栅极结构。 栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。 第二厚度大于第一厚度。 栅电极设置在第一和第二部分上。 在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。 还提供了一种制造该方法的方法。

公开(公告)号：US5840605A

公开(公告)日：1998-11-24

申请号：US47397

申请日：1993-04-19

Applicant: Hsiao-Chin Tuan

Inventor： Hsiao-Chin Tuan

IPC: H01L21/8242

CPC classification number: H01L27/10852

Abstract: A gate silicon oxide layer is formed on the silicon substrate. A doped layer of polysilicon is formed over the gate silicon oxide layer. The polysilicon layer is patterned to provide the gate electrodes of the transistor. Source/drain regions are formed through ion implantation followed by spacer formation. A node contact oxide is blanket deposited and an opening is formed therein to the silicon substrate at the location of the buried contact. A dual layer of polysilicon is deposited over the node contact oxide and within the opening to the substrate. This dual layer consists of a bottom layer of undoped polysilicon and a top layer of in-situ doped polysilicon wherein the relative thicknesses of the two layers have been determined to optimize both concentration of dopant at the surface of the capacitor node and junction depth. The substrate is annealed to drive in the buried junction. The dual polysilicon layers are patterned to form the capacitor node. A capacitor dielectric is deposited followed by an in-situ doped polysilicon layer which will form the top capacitor plate. An insulating layer is blanket deposited. An opening is made in the insulating layer to the capacitor plate at the boundary of the cell layer. The contact is completed by the deposition and patterning of a metal layer to complete construction of the capacitor, gate electrode, and source/drain structures with buried contacts.

Abstract translation: 在硅衬底上形成栅氧化硅层。 在栅极氧化硅层上形成掺杂多晶硅层。 图案化多晶硅层以提供晶体管的栅电极。 源极/漏极区域通过离子注入形成，然后形成间隔物。 节点接触氧化物是被覆盖的，并且在掩埋触点的位置处向硅衬底形成开口。 双层多晶硅沉积在节点接触氧化物上并且在开口内沉积到衬底上。 该双层由未掺杂多晶硅的底层和原位掺杂多晶硅的顶层组成，其中已确定两层的相对厚度以优化电容器节点表面处的掺杂剂的浓度和结深度。 将衬底退火以在掩埋结中驱动。 图案化双重多晶硅层以形成电容器节点。 沉积电容器电介质，然后沉积形成顶部电容器板的原位掺杂多晶硅层。 绝缘层被毯子沉积。 在电池层的边界处，在电容器板的绝缘层上形成开口。 通过金属层的沉积和图案化来完成接触，以完成具有埋入触点的电容器，栅极电极和源极/漏极结构的构造。

公开(公告)号：US5429714A

公开(公告)日：1995-07-04

申请号：US251191

申请日：1994-05-31

Applicant: Hsiao-Chin Tuan ,  Hu H. Chao

Inventor： Hsiao-Chin Tuan ,  Hu H. Chao

IPC: H01L21/32 ,  H01L21/00

CPC classification number: H01L21/32

Abstract: A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.

Abstract translation: 在硅晶片的表面上形成氧化硅隔离区的方法，所述硅晶片由晶圆上的薄氧化硅组成，杂质掺杂多晶硅层和氮化硅层组成。 通过图案化氮化硅层和掺杂多晶硅层的至少一部分来形成氧化掩模。 氧化硅场隔离区域通过使结构体经受热氧化环境而形成。 在一个连续蚀刻步骤中使用单一蚀刻剂除去氧化掩模，所述蚀刻剂例如以基本上相同的速率蚀刻氮化硅和多晶硅层的磷酸，以完成隔离区的形成，而不会点蚀单晶衬底。

公开(公告)号：US08704312B2

公开(公告)日：2014-04-22

申请号：US12652294

申请日：2010-01-05

Applicant: Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L24/16 ,  H01L24/48 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract translation: 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。

公开(公告)号：US08664718B2

公开(公告)日：2014-03-04

申请号：US13348463

申请日：2012-01-11

Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66659

Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.

Abstract translation: 功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。 栅极电介质和栅电极设置在半导体区域上。 与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。 电介质层具有在漂移区的顶表面上方并与其接触的部分。 导电场板在电介质层的上方。 源极区域和漏极区域在栅电极的相对侧上。 漏极区域与第一漂移区域接触。 底部金属层在场板上。

公开(公告)号：US08461647B2

公开(公告)日：2013-06-11

申请号：US12721045

申请日：2010-03-10

Applicant: Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

Inventor： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

IPC: H01L29/66

CPC classification number: H01L29/42368 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

Abstract translation: 提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。 该器件包括形成在半导体衬底上的半导体衬底和栅极结构。 栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。 第二厚度大于第一厚度。 栅电极设置在第一和第二部分上。 在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。 还提供了一种制造该方法的方法。

公开(公告)号：US08389348B2

公开(公告)日：2013-03-05

申请号：US12881505

申请日：2010-09-14

Applicant: Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

Inventor： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

IPC: H01L21/338

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.

Abstract translation: 在上述Si衬底上形成SiC结晶区的机理能够在同一衬底上形成GaN和GaN基器件的集成。 通过将碳注入到Si衬底的区域中，然后使衬底退火来形成SiC晶体区域。 在形成SiC晶体区域期间，使用注入停止层来覆盖Si器件区域。