公开(公告)号：US08158512B2

公开(公告)日：2012-04-17

申请号：US12141040

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Sean Fuxiong Zhang

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Sean Fuxiong Zhang

IPC分类号： H01L21/203

CPC分类号： C23C16/45529 ,  H01L21/28282 ,  H01L29/1608 ,  H01L29/42348 ,  H01L29/792

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：在ALD室内使第一前体气体流到半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 形成第一电介质层以覆盖离散化合物单层; 在第一介电层上形成第二第三单层; 并形成第二离散化合物单层; 以及形成第二电介质层以覆盖所述第一电介质层上方的所述第二离散化合物单层。 还提供了通过ALD方法形成的半导体器件。

公开(公告)号：US07709386B2

公开(公告)日：2010-05-04

申请号：US12141045

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/44

CPC分类号： H01L21/0228 ,  C23C16/45529 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/11563

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

摘要翻译： 提供了一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。 还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的介电层。

公开(公告)号：US20080315295A1

公开(公告)日：2008-12-25

申请号：US12132459

申请日：2008-06-03

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L29/792 ,  H01L21/311

CPC分类号： C23C16/04 ,  C23C16/45527 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/3185

摘要： Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

摘要翻译： 公开了原子层沉积方法和包括原子层的半导体器件，包括以下步骤：将半导体衬底放置在原子层沉积室中; 将第一前体气体供给到腔室内的半导体衬底，以在半导体衬底上形成第一离散单层; 向腔室内的半导体衬底供给惰性清洗气体以去除在半导体衬底上未形成第一离散单层的第一前体气体; 将第二前体气体供给到所述室中以与形成所述第一离散单层的所述第一前体气体反应，形成离散的原子尺寸岛; 以及将惰性吹扫气体供给到室内的半导体衬底以除去未与第一前体气体反应的第二前体气体和由第一和第二前体气体之间的反应产生的副产物。

公开(公告)号：US20080315292A1

公开(公告)日：2008-12-25

申请号：US12141040

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Seanfuxiong Zhang

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Seanfuxiong Zhang

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： C23C16/45529 ,  H01L21/28282 ,  H01L29/1608 ,  H01L29/42348 ,  H01L29/792

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：在ALD室内使第一前体气体流到半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 形成第一电介质层以覆盖离散化合物单层; 在第一介电层上形成第二第三单层; 并形成第二离散化合物单层; 以及形成第二电介质层以覆盖所述第一电介质层上方的所述第二离散化合物单层。 还提供了通过ALD方法形成的半导体器件。

公开(公告)号：US20080315293A1

公开(公告)日：2008-12-25

申请号：US12141045

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L21/0228 ,  C23C16/45529 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/11563

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。 还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的电介质层。

公开(公告)号：US08273639B2

公开(公告)日：2012-09-25

申请号：US12132459

申请日：2008-06-03

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/20

CPC分类号： C23C16/04 ,  C23C16/45527 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/3185

摘要： Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

摘要翻译： 公开了原子层沉积方法和包括原子层的半导体器件，包括以下步骤：将半导体衬底放置在原子层沉积室中; 将第一前体气体供给到腔室内的半导体衬底，以在半导体衬底上形成第一离散单层; 向腔室内的半导体衬底供给惰性清洗气体以去除在半导体衬底上未形成第一离散单层的第一前体气体; 将第二前体气体供给到所述室中以与形成所述第一离散单层的所述第一前体气体反应，形成离散的原子尺寸岛; 以及将惰性吹扫气体供给到室内的半导体衬底以除去未与第一前体气体反应的第二前体气体和由第一和第二前体气体之间的反应产生的副产物。

公开(公告)号：US20120168853A1

公开(公告)日：2012-07-05

申请号：US13419943

申请日：2012-03-14

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Seanfuxiong Zhang

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Seanfuxiong Zhang

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  C23C16/45529 ,  H01L29/1608 ,  H01L29/40117 ,  H01L29/42348

摘要： A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method.

摘要翻译： 一种半导体非易失性存储器（NVM）器件，包括：半导体衬底; 设置在半导体衬底上的中层电荷俘获层 - 介质层的三层堆叠结构; 设置在三层堆叠结构上方的栅极; 在三层堆叠结构的任一侧设置在半导体衬底中的源极和漏极; 其中电荷捕获层是包含通过原子层沉积（ALD）方法形成的一个或多个离散化合物簇的电介质层。

公开(公告)号：US08513079B2

公开(公告)日：2013-08-20

申请号：US12259144

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/792

摘要： A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P− polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P+ polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 提供一种具有薄膜晶体管（TFT）硅 - 氧化铝 - 硅（SAS）存储单元结构的器件。 该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。 介电层与第一表面相关联。 所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。 另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P-多晶硅层上的氧化铝层; 以及覆盖氧化铝层的至少一个控制栅极。 在具体实施例中，控制栅由高掺杂P +多晶硅制成。 提供了用于制造TFT SAS存储单元结构的方法，并且可以重复三维地集成结构。

公开(公告)号：US08415218B2

公开(公告)日：2013-04-09

申请号：US12259128

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/00 ,  C23C16/24 ,  H01L29/06 ,  H01L47/02 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/80 ,  H01L29/76 ,  H01L29/788 ,  H01L21/70

CPC分类号： H01L21/02381 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/78672

摘要： A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

摘要翻译： 提供了生长外延硅层的方法。 该方法包括提供包含氧封端的硅表面的衬底，并在氧封端的硅表面上形成第一个氢封端的硅表面。 此外，该方法包括通过原子层沉积（ALD）外延从由Ar流和闪光灯退火辅助的SiH 4热裂解基团连续形成在第一氢封端硅表面上的第二氢封端硅表面。 第二个氢封端的硅表面能够连续地由Ar流和闪光灯退火辅助的SiH 4热裂解基团通过ALD外延添加一层或多层硅。 在一个实施例中，该方法被应用于制造具有能够进行三维集成的薄膜晶体管（TFT）浮动栅极存储单元结构的器件。

公开(公告)号：US08105920B2

公开(公告)日：2012-01-31

申请号：US12259015

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/00

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L27/12 ,  H01L29/8616

摘要： A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 具有非晶硅（a-Si）金属 - 氧化铝半导体（MAS）存储单元结构的半导体器件。 该器件包括衬底，覆盖在衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域，其中n型a-Si的共面表面和电介质层。 另外，器件包括p-i-n a-Si二极管结。 该器件还包括在a-Si p-i-n二极管结上的氧化铝电荷俘获层和覆盖氧化铝层的金属控制栅极。 提供了一种用于制造a-Si MAS存储单元结构并且可以重复三维地集成结构的方法。