公开(公告)号：US20070023829A1

公开(公告)日：2007-02-01

申请号：US11491743

申请日：2006-07-24

申请人： Hugo Burke ,  David Jones ,  Ling Ma ,  Robert Montgomery

发明人： Hugo Burke ,  David Jones ,  Ling Ma ,  Robert Montgomery

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/2815 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734

摘要： A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

摘要翻译： 一种功率半导体器件，其包括沿栅极绝缘衬垫延伸的栅极衬垫和间隔两个栅极衬垫的绝缘块。

公开(公告)号：US20110284950A1

公开(公告)日：2011-11-24

申请号：US12800662

申请日：2010-05-20

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

摘要翻译： 公开了一种制造浅沟槽场效应晶体管（沟槽FET）的方法。 该方法包括在第一导电类型的半导体衬底内形成沟槽，沟槽包括侧壁和底部。 该方法还包括在沟槽中形成基本上均匀的栅极电介质，以及在所述沟槽内和所述栅极电介质上方形成栅电极。 该方法还包括在形成沟槽之后掺杂半导体衬底以形成第二导电类型的沟道区。 在一个实施例中，在形成栅极电介质之后并在形成栅电极之后执行掺杂步骤。 在另一个实施例中，掺杂步骤在形成栅极电介质之后，但在形成栅电极之前进行。 还公开了通过本发明方法形成的结构。

公开(公告)号：US08536645B2

公开(公告)日：2013-09-17

申请号：US13031505

申请日：2011-02-21

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

摘要翻译： 根据示例性实施例，沟槽场效应晶体管（沟槽FET）包括形成在半导体衬底中的沟槽，沟槽包括设置在其中的栅极电介质。 源极区域邻近沟槽设置。 沟槽FET还具有包括设置在沟槽中的下部的栅电极和在源极区域上横向延伸的骄傲部分。 硅化物源接触件可以沿着源极区域的侧壁垂直延伸。 此外，栅极电介质的一部分可以在半导体衬底上横向延伸。 沟槽FET还可以包括形成在栅电极的骄傲部分上的硅化物栅极接触。

公开(公告)号：US20120211825A1

公开(公告)日：2012-08-23

申请号：US13031505

申请日：2011-02-21

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

摘要翻译： 根据示例性实施例，沟槽场效应晶体管（沟槽FET）包括形成在半导体衬底中的沟槽，沟槽包括设置在其中的栅极电介质。 源极区域邻近沟槽设置。 沟槽FET还具有包括设置在沟槽中的下部的栅电极和在源极区域上横向延伸的骄傲部分。 硅化物源接触件可以沿着源极区域的侧壁垂直延伸。 此外，栅极电介质的一部分可以在半导体衬底上横向延伸。 沟槽FET还可以包括形成在栅电极的骄傲部分上的硅化物栅极接触。

公开(公告)号：US09653597B2

公开(公告)日：2017-05-16

申请号：US12800662

申请日：2010-05-20

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan ,  Igor Bol

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan ,  Igor Bol

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

公开(公告)号：US07423317B2

公开(公告)日：2008-09-09

申请号：US11491743

申请日：2006-07-24

申请人： Hugo R. G. Burke ,  David Paul Jones ,  Ling Ma ,  Robert Montgomery

发明人： Hugo R. G. Burke ,  David Paul Jones ,  Ling Ma ,  Robert Montgomery

IPC分类号： H01L29/739

CPC分类号： H01L29/7813 ,  H01L21/2815 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734

摘要： A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

摘要翻译： 一种功率半导体器件，其包括沿栅极绝缘衬垫延伸的栅极衬垫和间隔两个栅极衬垫的绝缘块。

公开(公告)号：US08860194B2

公开(公告)日：2014-10-14

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H01L23/495

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可以连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US20130301464A1

公开(公告)日：2013-11-14

申请号：US13979112

申请日：2012-02-16

申请人： Shengbin Wang ,  Xia Hu ,  Ling Ma

发明人： Shengbin Wang ,  Xia Hu ,  Ling Ma

IPC分类号： H04W48/18 ,  H04W24/10

CPC分类号： H04W48/18 ,  H04W24/10 ,  H04W36/0094 ,  H04W36/14 ,  H04W48/16

摘要： Method and device for measurement compensation for inter-system reselection and handover in a dual-mode terminal are disclosed. The method comprises: a GSM physical layer reporting measured RSCP and Ec/No values of a 3G neighbor cell to a radio resource management layer with inter-layer primitives; the radio resource management layer receiving the inter-layer primitives carrying the RSCP and Ec/No values reported by the physical layer, and performing measurement compensation for the inter-layer primitives in the radio resource management layer. Since the measurement compensation is performed in the radio resource management layer of the terminal, the terminal preferably resides on 3G network when detecting the 3G network. It can be applied to measurement compensation for the inter-system reselection and handover when 2G and 3G mobile communication systems co-exist. The terminal is more easily retained on the network of one of the systems and allowed to make a priority selection of the networks.

摘要翻译： 公开了用于双模终端中的系统间重选和切换的测量补偿的方法和装置。 该方法包括：GSM物理层向具有层间原语的无线资源管理层报告测量的RSCP和3G相邻小区的Ec / No值; 无线资源管理层接收携带由物理层报告的RSCP和Ec / No值的层间原语，并对无线资源管理层中的层间原语进行测量补偿。 由于在终端的无线资源管理层中进行测量补偿，所以在检测到3G网络时，终端优选地位于3G网络上。 当2G和3G移动通信系统共存时，可以应用于系统间重选和切换的测量补偿。 终端更容易保留在系统之一的网络上，并允许优先选择网络。

公开(公告)号：US08017494B2

公开(公告)日：2011-09-13

申请号：US12011290

申请日：2008-01-25

申请人： Ling Ma

发明人： Ling Ma

IPC分类号： H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/66734 ,  H01L29/7811

摘要： A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof.

摘要翻译： 一种用于制造在其终端区域中包括多个间隔开的沟槽的MOS器件的工艺。

公开(公告)号：US07465986B2

公开(公告)日：2008-12-16

申请号：US11211268

申请日：2005-08-25

申请人： Dev Alok Girdhar ,  Ling Ma ,  Steven T. Peake ,  David Paul Jones

发明人： Dev Alok Girdhar ,  Ling Ma ,  Steven T. Peake ,  David Paul Jones

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/861

摘要： A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

摘要翻译： 功率半导体器件包括形成在半导体本体内的多个沟槽，每个沟槽包括形成在其中的一个或多个电极。 具体地，根据本发明的实施例，半导体器件的多个沟槽可以包括一个或多个栅电极，可以包括一个或多个栅电极或一个或多个源电极，或者可以包括栅极和源极的组合 电极形成在其中。 沟槽和电极在半导体本体内可能具有不同的深度。