公开(公告)号：US08466546B2

公开(公告)日：2013-06-18

申请号：US11409298

申请日：2006-04-21

申请人： Andy Farlow ,  Mark Pavier ,  Andrew N. Sawle ,  George Pearson ,  Martin Standing

发明人： Andy Farlow ,  Mark Pavier ,  Andrew N. Sawle ,  George Pearson ,  Martin Standing

IPC分类号： H01L23/48

CPC分类号： H01L24/33 ,  H01L23/041 ,  H01L23/492 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/83801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/30105 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.

摘要翻译： 一种半导体封装，其包括优选为罐形状的导电夹子，半导体管芯和插入在所述管芯和所述罐体内部的导电堆叠，其包括导电平台和导电粘合体。

公开(公告)号：US08426952B2

公开(公告)日：2013-04-23

申请号：US13278695

申请日：2011-10-21

申请人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

发明人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

IPC分类号： H01L23/495 ,  H01L23/34

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/071 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

摘要翻译： 根据示例性实施例，堆叠半桥封装包括具有用于连接到高电压输入的控制漏极的控制晶体管，耦合到输出端子的控制源以及由驱动器IC驱动的控制栅极。 堆叠的半桥封装进一步包括具有用于连接到输出端子的同步漏极的同步晶体管，耦合到低电压输入的同步源，以及由驱动器IC驱动的同步栅极。 控制和同步晶体管堆叠在公共导电引线框架的相对侧上，公共导电引线框架将控制源与同步漏极电连接和机械耦合。 因此，公共导电引线框用作输出端子。

公开(公告)号：US20120181674A1

公开(公告)日：2012-07-19

申请号：US13278695

申请日：2011-10-21

申请人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

发明人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

IPC分类号： H01L25/07 ,  H01L23/495

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/071 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

摘要翻译： 根据示例性实施例，堆叠半桥封装包括具有用于连接到高电压输入的控制漏极的控制晶体管，耦合到输出端子的控制源以及由驱动器IC驱动的控制栅极。 堆叠的半桥封装进一步包括具有用于连接到输出端子的同步漏极的同步晶体管，耦合到低电压输入的同步源，以及由驱动器IC驱动的同步栅极。 控制和同步晶体管堆叠在公共导电引线框架的相对侧上，公共导电引线框架将控制源与同步漏极电连接和机械耦合。 因此，公共导电引线框用作输出端子。

公开(公告)号：US20120181624A1

公开(公告)日：2012-07-19

申请号：US13279052

申请日：2011-10-21

申请人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

发明人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

IPC分类号： H01L27/088

CPC分类号： H01L25/074 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45099

摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

摘要翻译： 根据示例性实施例，堆叠半桥封装包括控制晶体管，其具有用于连接到高电压输入的控制漏极，耦合到公共导电夹子的控制源和用于由驱动器IC驱动的控制栅极。 堆叠的半桥封装还包括具有用于连接到公共导电夹子的同步漏极的同步晶体管，耦合到低电压输入的同步源以及由驱动器IC驱动的同步栅极。 控制和同步晶体管堆叠在公共导电夹的相对侧上，其中公共导电夹将电源和机械耦合控制源与同步漏极，其中公共导电夹具有用于提供到输出端的电气和机械连接的导电腿 终端引线框架。

公开(公告)号：US08860194B2

公开(公告)日：2014-10-14

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H01L23/495

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可以连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US08674497B2

公开(公告)日：2014-03-18

申请号：US13278968

申请日：2011-10-21

申请人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

发明人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/074 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

摘要翻译： 根据示例性实施例，堆叠半桥封装包括具有用于连接到高电压输入的控制漏极的控制晶体管，耦合到输出端子的控制源以及由驱动器IC驱动的控制栅极。 堆叠的半桥封装还包括具有用于连接到输出端子的同步漏极的同步晶体管，耦合到低电压输入的同步源，以及由驱动器IC驱动的同步栅极。 载流层位于同步漏极上; 控制晶体管和同步晶体管彼此堆叠，其中载流层在同步漏极和控制源之间提供高电流连接。

公开(公告)号：US07285866B2

公开(公告)日：2007-10-23

申请号：US11146628

申请日：2005-06-07

申请人： Martin Standing ,  Andrew N Sawle

发明人： Martin Standing ,  Andrew N Sawle

IPC分类号： H01L29/41

CPC分类号： H01L23/047 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/492 ,  H01L24/37 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET. The MOSFET so received is oriented such that its drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like. The edges of the MOSFET so placed are spaced from the walls of the can. The space between the edges of the MOSFET and the walls of the can is filled with an insulating layer. A surface of the MOSFET is sub-flush below the plane of a substrate by 0.001-0.005 inches to reduce temperature cycling failures.

摘要翻译： 根据本发明的半导体封装包括金属罐，其在其内部空间中容纳MOSFET。 如此接收的MOSFET取向为使得其漏电极面向罐的底部，并且通过导电环氧树脂或焊料等层与其电连接。 所放置的MOSFET的边缘与罐的壁间隔开。 MOSFET的边缘和罐壁之间的空间填充有绝缘层。 MOSFET的表面在衬底的平面下方低于0.001-0.005英寸，以减少温度循环故障。

公开(公告)号：US09633951B2

公开(公告)日：2017-04-25

申请号：US11595206

申请日：2006-11-10

申请人： Mark Pavier ,  Andrew N. Sawle ,  Martin Standing

发明人： Mark Pavier ,  Andrew N. Sawle ,  Martin Standing

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/492 ,  H01L23/00 ,  H01L23/14

CPC分类号： H01L23/043 ,  H01L21/56 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/37 ,  H01L24/83 ,  H01L24/97 ,  H01L25/07 ,  H01L2224/0346 ,  H01L2224/0508 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/40252 ,  H01L2924/403 ,  H01L2924/40407 ,  H01L2224/82 ,  H01L2224/83

摘要： A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

公开(公告)号：US20140118032A1

公开(公告)日：2014-05-01

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H02M3/155

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US08680627B2

公开(公告)日：2014-03-25

申请号：US13279052

申请日：2011-10-21

申请人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

发明人： Eung San Cho ,  Chuan Cheah ,  Andrew N. Sawle

IPC分类号： H01L27/088

CPC分类号： H01L25/074 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45099

摘要： According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

摘要翻译： 根据示例性实施例，堆叠半桥封装包括控制晶体管，其具有用于连接到高电压输入的控制漏极，耦合到公共导电夹子的控制源和用于由驱动器IC驱动的控制栅极。 堆叠的半桥封装还包括具有用于连接到公共导电夹子的同步漏极的同步晶体管，耦合到低电压输入的同步源以及由驱动器IC驱动的同步栅极。 控制和同步晶体管堆叠在公共导电夹的相对侧上，其中公共导电夹将电源和机械耦合控制源与同步漏极，其中公共导电夹具有用于提供到输出端的电气和机械连接的导电腿 终端引线框架。