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    DOWN-SAMPLING CLOCK AND DATA RECOVERY CIRCUIT HAVING SELECTABLE RATE AND PHASE OUTPUT AND METHOD OF OPERATION THEREOF
    1.
    发明申请
    DOWN-SAMPLING CLOCK AND DATA RECOVERY CIRCUIT HAVING SELECTABLE RATE AND PHASE OUTPUT AND METHOD OF OPERATION THEREOF 有权
    具有可选择速率和相位输出的下采样时钟和数据恢复电路及其操作方法

    公开(公告)号：US20130322885A1

    公开(公告)日：2013-12-05

    申请号：US13486552

    申请日：2012-06-01

    申请人： Hungkei Chow ,  Dusan Suvakovic ,  Christophe Van Praet ,  Guy Torfs ,  Xin Yin ,  Zhisheng Li

    发明人： Hungkei Chow ,  Dusan Suvakovic ,  Christophe Van Praet ,  Guy Torfs ,  Xin Yin ,  Zhisheng Li

    IPC分类号： H04L7/033

    CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/087 ,  H04L25/06 ,  Y02D50/10

    摘要： A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.

    摘要翻译： 时钟和数据恢复（CDR）电路，一种从接收到的原始数据流中恢复时钟和数据的方法以及包含CDR电路的BI-PON光网络收发器（ONT）接收器前端的方法。 在一个实施例中，CDR电路包括：（1）具有压控振荡器的线路速率CDR电路，所述线路速率CDR电路被配置为以接收线路速率恢复原始数据流，（2）固定速率下变频， 采样器，其耦合到线路速率CDR电路并且被配置为基于固定速率对原始数据流进行下采样;以及（3）耦合到固定速率下采样器的可变速率下采样器， 基于可变速率对原始数据采样进行采样。

    Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof
    2.
    发明授权
    Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof 有权
    具有可选速率和相位输出的下采样时钟和数据恢复电路及其操作方法

    公开(公告)号：US08971718B2

    公开(公告)日：2015-03-03

    申请号：US13486552

    申请日：2012-06-01

    申请人： Hungkei Chow ,  Dusan Suvakovic ,  Christophe Van Praet ,  Guy Torfs ,  Xin Yin ,  Zhisheng Li

    发明人： Hungkei Chow ,  Dusan Suvakovic ,  Christophe Van Praet ,  Guy Torfs ,  Xin Yin ,  Zhisheng Li

    IPC分类号： H04B10/00 ,  H04L7/033 ,  H03L7/08 ,  H04L25/06 ,  H03L7/087

    CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/087 ,  H04L25/06 ,  Y02D50/10

    摘要： A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.

    摘要翻译： 时钟和数据恢复（CDR）电路，一种从接收到的原始数据流中恢复时钟和数据的方法以及包含CDR电路的BI-PON光网络收发器（ONT）接收器前端的方法。 在一个实施例中，CDR电路包括：（1）具有压控振荡器的线路速率CDR电路，线路速率CDR电路被配置为以接收线路速率恢复原始数据流，（2）固定速率下变频， 采样器，其耦合到线路速率CDR电路并且被配置为基于固定速率对原始数据流进行下采样;以及（3）耦合到固定速率下采样器的可变速率下采样器， 基于可变速率对原始数据采样进行采样。

    A/D converter comprising a voltage comparator device
    5.
    发明授权
    A/D converter comprising a voltage comparator device 有权
    A / D转换器包括电压比较器装置

    公开(公告)号：US07652600B2

    公开(公告)日：2010-01-26

    申请号：US12191059

    申请日：2008-08-13

    申请人： Geert Van der Plas ,  Johan Bauwelinck ,  Zhisheng Li ,  Guy Torfs ,  Jan Vandewege ,  Xin Yin

    发明人： Geert Van der Plas ,  Johan Bauwelinck ,  Zhisheng Li ,  Guy Torfs ,  Jan Vandewege ,  Xin Yin

    IPC分类号： H03M1/10

    CPC分类号： H03M1/1061 ,  H03M1/0809 ,  H03M1/0863 ,  H03M1/361

    摘要： The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.

    摘要翻译： 本发明公开了一种包括至少两个电压比较器装置的模拟 - 数字转换器。 每个电压比较器装置包括晶体管的差分结构，并且被布置为被馈送相同的输入信号并且通过差分结构中的不平衡来产生自己的内部参考电压，所述两个内部电压基准是不同的。 每个电压比较器被布置用于产生指示输入信号的数字近似的位位置的输出信号。

    ESD protection device with reduced clamping voltage
    6.
    发明授权
    ESD protection device with reduced clamping voltage 有权
    降低钳位电压的ESD保护器件

    公开(公告)号：US08873210B2

    公开(公告)日：2014-10-28

    申请号：US13607959

    申请日：2012-09-10

    申请人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    发明人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    IPC分类号： H02H3/22 ,  H02H9/04 ,  H01L27/02

    CPC分类号： H01L27/0259 ,  H02H9/046

    摘要： Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

    摘要翻译： 公开了一种ESD保护电路，其包括多个双极晶体管，即在第一和第二端子（T1，T2）之间的主ESD导电路径中的多个ESD导电晶体管（Q1，Q2，Q4） 包括至少一个驱动晶体管（Q3），所述至少一个驱动晶体管（Q3）并联连接到所述ESD导电晶体管（Q1）中的至少一个，并被提供用于在发生时向一个或多个ESD导电晶体管（Q3）传导驱动电流（Ib2） 的ESD事件。

    ESD Protection Device With Reduced Clamping Voltage
    7.
    发明申请
    ESD Protection Device With Reduced Clamping Voltage 有权
    具有降低钳位电压的ESD保护器件

    公开(公告)号：US20130063846A1

    公开(公告)日：2013-03-14

    申请号：US13607959

    申请日：2012-09-10

    申请人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    发明人： Ramses Pierco ,  Johan Bauwelinck ,  Xin Yin

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0259 ,  H02H9/046

    摘要： Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

    摘要翻译： 公开了一种ESD保护电路，其包括多个双极晶体管，即在第一和第二端子（T1，T2）之间的主ESD导电路径中的多个ESD导电晶体管（Q1，Q2，Q4） 包括至少一个驱动晶体管（Q3），所述至少一个驱动晶体管（Q3）并联连接到所述ESD导电晶体管（Q1）中的至少一个，并被提供用于在发生时向一个或多个ESD导电晶体管（Q3）传导驱动电流（Ib2） 的ESD事件。

    Patient Monitor Having Entertainment Functions and Control Method Thereof
    8.
    发明申请
    Patient Monitor Having Entertainment Functions and Control Method Thereof 有权
    具有娱乐功能的患者监护仪及其控制方法

    公开(公告)号：US20120095299A1

    公开(公告)日：2012-04-19

    申请号：US13133949

    申请日：2010-05-26

    申请人： Shuo Sun ,  Xin Yin

    发明人： Shuo Sun ,  Xin Yin

    IPC分类号： A61B5/00 ,  G09G5/00 ,  G06F3/02

    CPC分类号： A61B5/00 ,  A61B5/6898 ,  A61B5/7445 ,  A61B5/746 ,  G06F1/1649 ,  G06F19/3418 ,  H04H40/00

    摘要： The invention provides a patient monitor having entertainment functions and a control method thereof. If a user initiates the entertainment functions of the patient monitor having entertainment functions, a system thereof sends an entertainment signal to an entertainment signal processing unit, the entertainment signal is then processed to display an image on an entertainment specific display apparatus, and sound playing is achieved via an entertainment specific loudspeaker; the system sends a parameter signal to a parameter signal processing unit in real time, the parameter signal is then processed to display real-time measurement values and waveforms of parameters on a monitor specific display apparatus, and playing of various sounds is achieved via a monitor specific loudspeaker; an alarm processing unit detects, in real-time, whether the physiological characteristics of patient meet the alarm condition, and once the condition is met, alarm is triggered immediately; with the patient monitor of the invention, patients can enjoy some entertainment activities for mental relaxation while lying on the bed without having an impact on normal real-time monitor for patients.

    摘要翻译： 本发明提供一种具有娱乐功能的患者监视器及其控制方法。 如果用户发起具有娱乐功能的患者监视器的娱乐功能，则其系统向娱乐信号处理单元发送娱乐信号，然后处理娱乐信号以在娱乐专用显示装置上显示图像，并且声音播放是 通过娱乐专用扬声器实现; 系统实时向参数信号处理单元发送参数信号，然后处理参数信号，在监视器特定显示装置上显示实时测量值和参数波形，并通过监视器实现各种声音的播放 特定扬声器; 报警处理单元实时检测患者的生理特征是否符合报警状态，一旦满足条件，则立即触发报警; 利用本发明的患者监护仪，患者可以在躺在床上享受一些精神放松的娱乐活动，而不会对患者的正常实时监测产生影响。

    Apparatus and method for realizing gray levels of LCD
    9.
    发明申请
    Apparatus and method for realizing gray levels of LCD 有权

    公开(公告)号：US20060103617A1

    公开(公告)日：2006-05-18

    申请号：US11207651

    申请日：2005-08-18

    申请人： Xin Yin ,  Hyung Kim

    发明人： Xin Yin ,  Hyung Kim

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/2081 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2320/0276

    摘要： Disclosed is an apparatus and a method, in which gray levels are realized in such a manner that a pixel is supplied with a constant current instead of a voltage and charging duration (required for inputting data until a gate is turned on/off) is time-divided by the number of gray levels to be realized. The apparatus includes a current supplier for supplying a current filling a pixel, a buffer for latching display data, an adder for adding currently-input display data and display data latched the buffer, a pulse generator for receiving data outputted from the adder and delivering a switch-on pulse having a pulse width corresponding to the outputted data to the current supplier, and a controller for controlling the current supplier, the adder, and the pulse generator.