LIGHT EMITTING DEVICE, PACKAGE, AND SYSTEM
    2.
    发明申请
    LIGHT EMITTING DEVICE, PACKAGE, AND SYSTEM 有权
    发光装置,包装和系统

    公开(公告)号:US20100276726A1

    公开(公告)日:2010-11-04

    申请号:US12772532

    申请日:2010-05-03

    IPC分类号: H01L33/12 H01L33/48

    摘要: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

    摘要翻译: 发光器件包括第一导电类型的第一半导体层,与第一半导体层相邻的有源层,第二导电类型的第二半导体层,并且邻近有源层设置钝化层, 活性层的表面。 钝化层可以是第一导电类型,第二导电类型或第一未掺杂半导体层之一的半导体层。 第一电极可以耦合到第一半导体层,并且第二电极可以耦合到第二半导体层。

    Light emitting device, package, and system
    3.
    发明授权
    Light emitting device, package, and system 有权
    发光器件,封装和系统

    公开(公告)号:US08232566B2

    公开(公告)日:2012-07-31

    申请号:US12772532

    申请日:2010-05-03

    IPC分类号: H01L33/00

    摘要: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

    摘要翻译: 发光器件包括第一导电类型的第一半导体层,与第一半导体层相邻的有源层,第二导电类型的第二半导体层,并且邻近有源层设置钝化层, 活性层的表面。 钝化层可以是第一导电类型,第二导电类型或第一未掺杂半导体层之一的半导体层。 第一电极可以耦合到第一半导体层,并且第二电极可以耦合到第二半导体层。

    Light emitting device with air bars and method of manufacturing the same
    4.
    发明授权
    Light emitting device with air bars and method of manufacturing the same 失效
    具有气棒的发光装置及其制造方法

    公开(公告)号:US08460949B2

    公开(公告)日:2013-06-11

    申请号:US12648358

    申请日:2009-12-29

    IPC分类号: H01L33/00

    摘要: Disclosed are a light emitting device having at least one air bar capable of improving light extracting efficiency and a method of manufacturing the same. With the present invention, there is provided a method of manufacturing a light emitting device including a semiconductor layer(s) having an air-bar layer(s) with a plurality of air bars. The method includes at least one process cycle for forming the semiconductor layer(s). The process cycle includes: forming a patterning thin-film layer on a substrate or a thin-film layer; forming on the patterning thin-film layer an etching guide pattern and an air-bar pattern connected to the etching guide pattern; forming a semiconductor layer(s) on the patterns and exposing the etching guide pattern; wet-etch the exposed etching guide pattern by using a wet-etching solution; and etch the air-bar pattern connected to the etching guide pattern.

    摘要翻译: 公开了具有能够提高光提取效率的至少一个气棒的发光装置及其制造方法。 通过本发明,提供一种制造发光器件的方法,该发光器件包括具有多个气棒的空气棒层的半导体层。 该方法包括用于形成半导体层的至少一个工艺循环。 工艺循环包括:在衬底或薄膜层上形成图案化薄膜层; 在图案化薄膜层上形成蚀刻引导图案和连接到蚀刻引导图案的空气棒图案; 在所述图案上形成半导体层并暴露所述蚀刻引导图案; 通过使用湿蚀刻溶液湿蚀刻暴露的蚀刻导向图案; 并蚀刻连接到蚀刻引导图案的气条图案。

    Light Emitting Device with Air Bars and Method of Manufacturing the Same
    5.
    发明申请
    Light Emitting Device with Air Bars and Method of Manufacturing the Same 失效
    带空气棒的发光装置及其制造方法

    公开(公告)号:US20100163906A1

    公开(公告)日:2010-07-01

    申请号:US12648358

    申请日:2009-12-29

    IPC分类号: H01L33/00

    摘要: Disclosed are a light emitting device having at least one air bar capable of improving light extracting efficiency and a method of manufacturing the same. With the present invention, there is provided a method of manufacturing a light emitting device including a semiconductor layer(s) having an air-bar layer(s) with a plurality of air bars. The method includes at least one process cycle for forming the semiconductor layer(s). The process cycle includes: forming a patterning thin-film layer on a substrate or a thin-film layer; forming on the patterning thin-film layer an etching guide pattern and an air-bar pattern connected to the etching guide pattern; forming a semiconductor layer(s) on the patterns and exposing the etching guide pattern; wet-etch the exposed etching guide pattern by using a wet-etching solution; and etch the air-bar pattern connected to the etching guide pattern.

    摘要翻译: 公开了具有能够提高光提取效率的至少一个气棒的发光装置及其制造方法。 通过本发明,提供一种制造发光器件的方法,该发光器件包括具有多个气棒的空气棒层的半导体层。 该方法包括用于形成半导体层的至少一个工艺循环。 工艺循环包括:在衬底或薄膜层上形成图案化薄膜层; 在图案化薄膜层上形成蚀刻引导图案和连接到蚀刻引导图案的空气棒图案; 在所述图案上形成半导体层并暴露所述蚀刻引导图案; 通过使用湿蚀刻溶液湿蚀刻暴露的蚀刻导向图案; 并蚀刻连接到蚀刻引导图案的气条图案。

    Circuit technique to prevent device overstress
    6.
    发明授权
    Circuit technique to prevent device overstress 有权
    电路技术防止器件过载

    公开(公告)号:US07619444B1

    公开(公告)日:2009-11-17

    申请号:US11299080

    申请日:2005-12-08

    IPC分类号: H03K19/0175 H03K19/094

    CPC分类号: H03K19/017545

    摘要: Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.

    摘要翻译: 确保一个或多个电路组件的技术和电路由于核心逻辑而不会受到高于其额定电压容限的电压电平,并且提供了在不同时间达到最终电压电平的I / O逻辑电源电压。 根据一些实施例,内部电压供应检测电路可以监视为产生用于编程电压调节器的控制信号的核心逻辑供电的电压电平的电平。 响应于确定核心逻辑电压电源低于预定电平,感测电路可以产生一个或多个调节电压信号以覆盖由电压调节器产生的调节电压信号。

    Circuit technique to achieve power up tristate on a memory bus
    7.
    发明授权
    Circuit technique to achieve power up tristate on a memory bus 有权
    电路技术在内存总线上实现上电三态

    公开(公告)号:US07541835B1

    公开(公告)日:2009-06-02

    申请号:US11299081

    申请日:2005-12-08

    IPC分类号: H03K19/00

    摘要: Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.

    摘要翻译: 确保未定义的控制信号的技术和电路不会由于核心逻辑而无意地驱动到总线上,并且提供了在不同时间达到最终电压电平的I / O逻辑电源电压。 根据一些实施例,内部电压检测电路可以监视为产生要在I / O焊盘上驱动的控制信号的核心逻辑供电的电压电平的电平。 感测电路可以产生用于保持I / O焊盘处于高阻抗状态的一个或多个控制信号。

    System and method for redundancy implementation in a semiconductor device

    公开(公告)号:US06556490B2

    公开(公告)日:2003-04-29

    申请号:US10099750

    申请日:2002-03-15

    IPC分类号: G11C700

    摘要: A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

    Unit for maintaining information regarding the state of a device during
battery power
    9.
    发明授权
    Unit for maintaining information regarding the state of a device during battery power 失效
    用于在电池供电期间维护有关设备状态的信息的单元

    公开(公告)号:US5801457A

    公开(公告)日:1998-09-01

    申请号:US749615

    申请日:1996-11-18

    摘要: A unit for maintaining the value of information regarding the state of a device during battery power includes one local latch per bit of state to be maintained. The latch is powered by a switched power supply which switches between main and battery power supplies. The latch latches the value of the bit of state when the value of the bit of state is valid and the power of the device is significant and maintains the value otherwise, typically during battery operation.

    摘要翻译: 在电池供电期间用于维持关于装置的状态的信息的值的单元包括要维持的每位状态的一个本地锁存器。 闩锁由在主电源和电池电源之间切换的开关电源供电。 当状态位的值有效并且器件的电源有效并且通常在电池操作期间保持其它值时,锁存器锁存状态位的值。