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1.发明申请公开(公告)号：US20210344349A1
公开(公告)日：2021-11-04
申请号：US17221166
申请日：2021-04-02
申请人： Imec vzw
发明人： Ewout Martens , Davide Dermit , Jan Craninckx
IPC分类号： H03M1/06
摘要： An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.
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公开(公告)号：US11128326B2
公开(公告)日：2021-09-21
申请号：US17098178
申请日：2020-11-13
发明人： Johan Nguyen , Khaled Khalaf , Pierre Wambacq , Jan Craninckx
摘要： A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.
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公开(公告)号：US10230347B2
公开(公告)日：2019-03-12
申请号：US15217927
申请日：2016-07-22
摘要： A system having a tunable impedance network and a method of tuning a tunable impedance network are disclosed. In one aspect, a telecommunications device comprises an electrical-balance duplexer (EBD) circuit coupled to at least one output node of a transmit path (TXin), an antenna, and at least one input node of a receive path (RXout), wherein the EBD circuit is configured to isolate the transmit path from the receive path by signal cancellation, and a balancing network (Zbal) as part of the EBD circuit. In one embodiment, the balancing network is an integrated tunable impedance network configured to provide an impedance that matches a target impedance (Zant) associated with the antenna at a first frequency and simultaneously at a second, different frequency. The network comprises a first portion and a second portion, the first portion reducing the influence of the tuning of the second portion at the first frequency. In some embodiments, the network preferably comprises no explicit resistors.
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公开(公告)号：US20170179976A1
公开(公告)日：2017-06-22
申请号：US15369777
申请日：2016-12-05
申请人： IMEC VZW
IPC分类号： H03M3/00
摘要： A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.
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公开(公告)号：US09349484B2
公开(公告)日：2016-05-24
申请号：US14808267
申请日：2015-07-24
申请人： IMEC VZW
发明人： Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
CPC分类号： G11C27/02 , H03M1/1245
摘要： The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
摘要翻译： 本公开涉及一种采样和保持电路，包括：晶体管，被布置用于在采样模式和保持模式之间切换;以及自举电路，布置成用于在采样模式中保持源极端子和栅极端子之间的电压电平 晶体管与源极端子处的电压无关，并且被设置为在保持模式下关断晶体管。 引导电路包括自举电容，其布置成在保持模式期间被预充电到给定电压，自举电容在采样模式期间连接在源极端子和栅极端子之间。 在一个示例中，自举电路包括用于产生给定电压的开关电容器电荷泵。
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公开(公告)号：US20230299478A1
公开(公告)日：2023-09-21
申请号：US18185181
申请日：2023-03-16
申请人： IMEC VZW
发明人： Yang Zhang , Jan Craninckx , Pierre Wambacq , Giuseppe Gramegna
IPC分类号： H01Q3/34 , H01P1/213 , H01P5/12 , H04B7/0408
CPC分类号： H01Q3/34 , H01P1/213 , H01P5/12 , H04B7/0408
摘要： A phased array transceiver element comprises a local oscillator stage for generating beamformed in-phase and quadrature local oscillator signals, the local oscillator stage comprising a phase shifter connectable to a reference frequency source and applying a first phase shift; a primary frequency multiplier input from the phase shifter and applying a primary frequency multiplication factor; a phase-splitting arrangement input from the primary frequency multiplier and having a first output and a second output, the phase-splitting arrangement applying a second phase shift at the first output and a third phase shift at the second output; a first secondary frequency multiplier input from the first output of the phase-splitting arrangement, having an output for the in-phase local oscillator signal, and applying a secondary frequency multiplication factor; and a second secondary frequency multiplier input from the second output of the phase-splitting arrangement, having an output for the quadrature local oscillator signal, and applying the secondary frequency multiplication factor.
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7.发明授权公开(公告)号：US11476858B2
公开(公告)日：2022-10-18
申请号：US17221166
申请日：2021-04-02
申请人： Imec vzw
发明人： Ewout Martens , Davide Dermit , Jan Craninckx
摘要： An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.
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公开(公告)号：US20210181775A1
公开(公告)日：2021-06-17
申请号：US17123299
申请日：2020-12-16
申请人： IMEC VZW
摘要： A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.
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公开(公告)号：US20210152197A1
公开(公告)日：2021-05-20
申请号：US17098178
申请日：2020-11-13
发明人： Johan Nguyen , Khaled Khalaf , Pierre Wambacq , Jan Craninckx
摘要： A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.
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公开(公告)号：US20190190531A1
公开(公告)日：2019-06-20
申请号：US16218916
申请日：2018-12-13
申请人： IMEC vzw
发明人： Ewout Martens , Benjamin Hershberg , Jan Craninckx
IPC分类号： H03M1/46
摘要： A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.
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