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    Telecommunications device comprising an EBD circuit, a tunable impedance network and a method for tuning a tunable impedance network
    2.
    发明授权
    Telecommunications device comprising an EBD circuit, a tunable impedance network and a method for tuning a tunable impedance network 有权

    公开(公告)号：US10230347B2

    公开(公告)日：2019-03-12

    申请号：US15217927

    申请日：2016-07-22

    申请人： IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

    发明人： Benjamin Hershberg ,  Barend Wilhelmus Marinus Van Liempd ,  Jan Craninckx

    IPC分类号： H03H7/38 ,  H03H7/46 ,  H04B1/18 ,  H04B1/52

    摘要： A system having a tunable impedance network and a method of tuning a tunable impedance network are disclosed. In one aspect, a telecommunications device comprises an electrical-balance duplexer (EBD) circuit coupled to at least one output node of a transmit path (TXin), an antenna, and at least one input node of a receive path (RXout), wherein the EBD circuit is configured to isolate the transmit path from the receive path by signal cancellation, and a balancing network (Zbal) as part of the EBD circuit. In one embodiment, the balancing network is an integrated tunable impedance network configured to provide an impedance that matches a target impedance (Zant) associated with the antenna at a first frequency and simultaneously at a second, different frequency. The network comprises a first portion and a second portion, the first portion reducing the influence of the tuning of the second portion at the first frequency. In some embodiments, the network preferably comprises no explicit resistors.

    Multiplying digital-to-analog conversion circuit
    4.
    发明授权
    Multiplying digital-to-analog conversion circuit 有权

    公开(公告)号：US10574255B2

    公开(公告)日：2020-02-25

    申请号：US16181222

    申请日：2018-11-05

    申请人： IMEC vzw

    发明人： Benjamin Hershberg ,  Jan Craninckx ,  Ewout Martens

    IPC分类号： H03M1/66 ,  H03M1/46 ,  H03M1/44 ,  H03F3/00 ,  H03M1/16 ,  H03F3/45 ,  H03M1/12

    摘要： A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

    Analog-to-digital converters
    5.
    发明授权
    Analog-to-digital converters 有权

    公开(公告)号：US10484000B2

    公开(公告)日：2019-11-19

    申请号：US16218916

    申请日：2018-12-13

    申请人： IMEC vzw

    发明人： Ewout Martens ,  Benjamin Hershberg ,  Jan Craninckx

    IPC分类号： H03M1/12 ,  H03M1/46

    摘要： A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.

    ANALOG-TO-DIGITAL CONVERTERS
    7.
    发明申请
    ANALOG-TO-DIGITAL CONVERTERS 审中-公开

    公开(公告)号：US20190190531A1

    公开(公告)日：2019-06-20

    申请号：US16218916

    申请日：2018-12-13

    申请人： IMEC vzw

    发明人： Ewout Martens ,  Benjamin Hershberg ,  Jan Craninckx

    IPC分类号： H03M1/46

    CPC分类号： H03M1/46 ,  H03M1/462 ,  H03M1/468

    摘要： A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.

    Input circuit for a dynamic comparator
    9.
    发明授权
    Input circuit for a dynamic comparator 有权

    公开(公告)号：US10090852B2

    公开(公告)日：2018-10-02

    申请号：US15826668

    申请日：2017-11-29

    申请人： IMEC VZW

    发明人： Ewout Martens ,  Benjamin Hershberg ,  Jan Craninckx

    IPC分类号： H03M1/34 ,  H03M1/38 ,  H03H19/00 ,  H03K5/24 ,  H03F3/45 ,  H03M1/36

    摘要： The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.