公开(公告)号：US11856789B2

公开(公告)日：2023-12-26

申请号：US17368686

申请日：2021-07-06

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Po-Chun Yeh ,  Pei-Jer Tzeng

IPC: H10B53/30 ,  G11C11/22

CPC classification number: H10B53/30 ,  G11C11/22 ,  H01L2924/1441

Abstract: A ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer. The ferroelectric composite layer includes a first electrode layer, a second electrode layer, a ferroelectric layer and an antiferroelectric layer. The first electrode layer is opposite to the second electrode layer, and the ferroelectric layer and the antiferroelectric layer are disposed between the first electrode layer and the second electrode layer.

公开(公告)号：US11217661B2

公开(公告)日：2022-01-04

申请号：US16842589

申请日：2020-04-07

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Chih-Yao Wang ,  Hsin-Yun Yang

IPC: H01L49/02 ,  H01L27/11502 ,  H01L27/11507 ,  G11C11/22

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

公开(公告)号：US11017830B1

公开(公告)日：2021-05-25

申请号：US16907101

申请日：2020-06-19

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Hsin-Yun Yang

IPC: G11C11/22

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of (110) or (220), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of (110) or (220), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of (111).

公开(公告)号：US10833091B2

公开(公告)日：2020-11-10

申请号：US16270706

申请日：2019-02-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Chih-Yao Wang ,  Hsin-Yun Yang

IPC: H01L27/11507 ,  G11C11/22 ,  H01L49/02

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.

公开(公告)号：US10074533B1

公开(公告)日：2018-09-11

申请号：US15723390

申请日：2017-10-03

Applicant: Industrial Technology Research Institute

Inventor： Po-Chun Yeh ,  Kan-Hsueh Tsai ,  Chuan-Wei Tsou ,  Heng-Yuan Lee ,  Hsueh-Hsing Liu ,  Han-Chieh Ho ,  Yi-Keng Fu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/267 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/02035 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 μm and a height between 1 and 500 μm.

公开(公告)号：US20140043226A1

公开(公告)日：2014-02-13

申请号：US13937242

申请日：2013-07-09

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wei-Yen Lee ,  Po-Chun Yeh ,  Heng-Yin Chen

IPC: G06F3/03

CPC classification number: G06F3/03 ,  G06F1/1643 ,  G06F1/1652 ,  G06F1/1677 ,  G06F1/1694 ,  G06F3/0416 ,  G06F2200/1614

Abstract: A portable device and associated control method are provided. The portable device includes a foldable display panel. The control method includes steps of: detecting a folding operation is applied to the display panel; retrieving at least one folding signal; converting a display region of the display panel from an original size to a folded size according to the at least one folding signal; and the display panel displaying an image according to the converted display region. The display panel selects a corresponding folding coordinate system according to the converted display region.

Abstract translation: 提供了一种便携式设备和相关的控制方法。 便携式设备包括可折叠显示面板。 控制方法包括以下步骤：检测折叠操作被施加到显示面板; 检索至少一个折叠信号; 根据所述至少一个折叠信号将所述显示面板的显示区域从原始大小转换成折叠尺寸; 并且所述显示面板根据所转换的显示区域显示图像。 显示面板根据转换的显示区域选择相应的折叠坐标系。

公开(公告)号：US20250063772A1

公开(公告)日：2025-02-20

申请号：US18940769

申请日：2024-11-07

Applicant: Industrial Technology Research Institute

Inventor： Po-Chun Yeh ,  Hsiang-Chun Wang

IPC: H01L29/06 ,  H01L23/473 ,  H01L29/08 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

公开(公告)号：US10720521B2

公开(公告)日：2020-07-21

申请号：US16359345

申请日：2019-03-20

Applicant: Industrial Technology Research Institute

Inventor： Jung-Tse Tsai ,  Po-Chun Yeh ,  Chien-Hua Hsu ,  Po-Tsung Tu

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/12

Abstract: An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

公开(公告)号：US10014375B1

公开(公告)日：2018-07-03

申请号：US15722967

申请日：2017-10-02

Applicant: Industrial Technology Research Institute

Inventor： Chuan-Wei Tsou ,  Po-Chun Yeh ,  Heng-Yuan Lee

IPC: H01L29/20 ,  H01L29/10 ,  H01L29/778

CPC classification number: H01L29/1095 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66462 ,  H01L29/7786

Abstract: A III-nitride based semiconductor structure includes a substrate; a buffer layer disposed above the substrate; a first gallium nitrite (GaN) layer disposed above the buffer layer and including p-type GaN; a second GaN layer disposed on the first GaN layer and including at least a first region and a second region; a channel layer disposed above the second GaN layer; a barrier layer disposed above the channel layer; and a gate electrode disposed above the barrier layer. The first region of the second GaN layer is positioned correspondingly to the gate electrode and includes n-type GaN having a first doping concentration. The second region of the second GaN layer (such as the lateral portion of the second GaN layer) is positioned correspondingly to the areas outsides the gate electrode and includes n-type GaN having a second doping concentration larger than the first doping concentration.

公开(公告)号：US20230147806A1

公开(公告)日：2023-05-11

申请号：US17545996

申请日：2021-12-08

Applicant: Industrial Technology Research Institute

Inventor： Shang-Chun Chen ,  Po-Chun Yeh ,  Pei-Jer Tzeng

IPC: H01L23/528 ,  H01L23/66 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L23/66 ,  H01L23/5226 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7682 ,  H01L29/7787

Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.