公开(公告)号：US10068893B2

公开(公告)日：2018-09-04

申请号：US14725800

申请日：2015-05-29

Applicant: Infineon Technologies AG

Inventor： Jens Schneider ,  Klaus Roeschlau ,  Harald Gossner

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H02H9/04

Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

公开(公告)号：US09087892B2

公开(公告)日：2015-07-21

申请号：US14028403

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract translation: 在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。 第二掺杂类型与第一掺杂类型相反。 逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。 该装置还包括在逆行井上具有第二掺杂型的漏极区。 延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。 隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。 漏区的长度大于隔离区的深度。

公开(公告)号：US20130140626A1

公开(公告)日：2013-06-06

申请号：US13740048

申请日：2013-01-11

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0266 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.

公开(公告)号：US10374068B2

公开(公告)日：2019-08-06

申请号：US15403998

申请日：2017-01-11

Applicant: Infineon Technologies AG ,  Indian Institute of Technology Bombay

Inventor： Harald Gossner ,  Ramgopal Rao ,  Ram Asra

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/88 ,  H01L29/739 ,  H01L29/786 ,  H01L21/265 ,  H01L29/06 ,  H01L29/165

Abstract: Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

公开(公告)号：US09368573B2

公开(公告)日：2016-06-14

申请号：US14139888

申请日：2013-12-24

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

Abstract: In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a first source/drain region, forming a second source/drain region, forming an active region electrically coupled between the first source/drain region and the second source/drain region, forming a trench disposed between the second source/drain region and at least a portion of the active region, forming a first isolation layer disposed over the bottom and the sidewalls of the trench, forming electrically conductive material disposed over the isolation layer in the trench, forming a second isolation layer disposed over the active region, and forming a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.

Abstract translation: 在各种实施例中，提供了一种用于制造半导体器件的方法。 制造半导体器件的方法可以包括形成第一源极/漏极区域，形成第二源极/漏极区域，形成电耦合在第一源极/漏极区域与第二源极/漏极区域之间的有源区域，形成沟槽 在所述第二源极/漏极区域和所述有源区域的至少一部分之间形成设置在所述沟槽的底部和所述侧壁上的第一隔离层，形成设置在所述沟槽中的所述隔离层上方的导电材料，形成第二隔离层 层，设置在有源区上方，并且形成设置在第二隔离层上的栅极区。 导电材料可以耦合到电接触。

公开(公告)号：US20140113423A1

公开(公告)日：2014-04-24

申请号：US14139888

申请日：2013-12-24

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

Abstract: In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a first source/drain region, forming a second source/drain region, forming an active region electrically coupled between the first source/drain region and the second source/drain region, forming a trench disposed between the second source/drain region and at least a portion of the active region, forming a first isolation layer disposed over the bottom and the sidewalls of the trench, forming electrically conductive material disposed over the isolation layer in the trench, forming a second isolation layer disposed over the active region, and forming a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.

Abstract translation: 在各种实施例中，提供了一种用于制造半导体器件的方法。 制造半导体器件的方法可以包括形成第一源极/漏极区域，形成第二源极/漏极区域，形成电耦合在第一源极/漏极区域与第二源极/漏极区域之间的有源区域，形成沟槽 在所述第二源极/漏极区域和所述有源区域的至少一部分之间形成设置在所述沟槽的底部和所述侧壁上的第一隔离层，形成设置在所述沟槽中的所述隔离层上方的导电材料，形成第二隔离层 层，设置在有源区上方，并且形成设置在第二隔离层上的栅极区。 导电材料可以耦合到电接触。

公开(公告)号：US20170125556A1

公开(公告)日：2017-05-04

申请号：US15403998

申请日：2017-01-11

Applicant: Infineon Technologies AG ,  Indian Institute of Technology Bombay

Inventor： Harald Gossner ,  Ramgopal Rao ,  Ram Asra

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0895 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78696 ,  H01L29/88

Abstract: Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

公开(公告)号：US20150262993A1

公开(公告)日：2015-09-17

申请号：US14725800

申请日：2015-05-29

Applicant: Infineon Technologies AG

Inventor： Jens Schneider ,  Klaus Roeschlau ,  Harald Gossner

IPC: H01L27/02 ,  H01L29/78 ,  H02H9/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/732 ,  H01L29/06

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/732 ,  H01L29/7833 ,  H02H9/041

Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

公开(公告)号：US20130240992A1

公开(公告)日：2013-09-19

申请号：US13891221

申请日：2013-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Harald Gossner ,  Christian Russ

IPC: H01L23/60

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection element may include: a fin structure including a first connection region having a first conductivity type, a second connection region having a second conductivity type, first and second body regions formed between the connection regions, the first body region having the second conductivity type and formed adjacent to the first connection region, the second body region having the first conductivity type and formed adjacent to the second connection region, the body regions having a lower dopant concentration than the connection regions, a diffusion region formed between the body regions and having substantially the same dopant concentration as at least one of the first and second connection regions; a gate region on or above the first body region or the second body region; a gate control device electrically coupled to the gate region and configured to control at least one electrical potential applied to the gate region.

Abstract translation: ESD保护元件可以包括：翅片结构，其包括具有第一导电类型的第一连接区域，具有第二导电类型的第二连接区域，形成在连接区域之间的第一和第二主体区域，具有第二导电性的第一体区域 并且与第一连接区域相邻地形成，第二主体区域具有第一导电类型并且与第二连接区域相邻地形成，具有比连接区域低的掺杂剂浓度的体区域，形成在体区域之间的扩散区域和 具有与所述第一和第二连接区域中的至少一个基本上相同的掺杂剂浓度; 第一体区域或第二体区域上方的栅极区域; 门控制装置，其电耦合到栅极区域并且被配置为控制施加到栅极区域的至少一个电势。

公开(公告)号：US08531807B2

公开(公告)日：2013-09-10

申请号：US13676748

申请日：2012-11-14

Applicant: Infineon Technologies AG

Inventor： Wolfgang Soldner ,  Gernot Langguth ,  Christian Russ ,  Harald Gossner

IPC: H02H9/00 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L2924/0002 ,  H03K17/08122 ,  H01L2924/00

Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.

Abstract translation: 本公开的实施例涉及静电放电（ESD）保护技术。 例如，一些实施例包括可变电阻器，其选择性地将来自第一电路节点的输入ESD脉冲的功率分流到第二电路节点并远离半导体器件。 提供给可变电阻器的控制电压使得晶体管在只有亚阈值电流（如果有的话）流动的完全关闭模式之间改变; 其中最大量的电流流动的完全启动模式; 以及其中中间和时变量的电流流动的模拟模式。 特别地，模拟模式允许ESD保护装置比先前可实现的更精确地分流功率，使得ESD保护装置可以保护半导体器件免受ESD脉冲。