公开(公告)号：US20140110840A1

公开(公告)日：2014-04-24

申请号：US13736553

申请日：2013-01-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maciej Wojnowski ,  Walter Hartner ,  Ottmar Geitner ,  Gottfried Beer ,  Klaus Pressel ,  Mehran Pour Mousavi

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17519 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01Q23/00 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01064 ,  H01L2924/01044 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract translation: 在本发明的一个实施例中，半导体封装包括具有第一主表面和相对的第二主表面的衬底。 芯片设置在基板中。 芯片包括在第一主表面处的多个接触垫。 第一天线结构设置在第一主表面处。 反射器设置在第二主表面处。

公开(公告)号：US20150117862A1

公开(公告)日：2015-04-30

申请号：US14067640

申请日：2013-10-30

Applicant: Infineon Technologies AG

Inventor： Saverio Trotta ,  Jagjit Singh Bal ,  Maciej Wojnowski ,  Ernst Seler ,  Mehran Pour Mousavi

IPC: H01P3/12 ,  H04B10/2575 ,  H05K1/18 ,  H04B10/572 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01P5/107 ,  H01P3/12 ,  H04B10/2575 ,  H04B10/572 ,  H05K1/0206 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/181 ,  H05K3/4697

Abstract: According to an embodiment, a circuit board includes a signal line including at least portion of a first conductive layer that has a first portion extending over a cavity in the circuit board from a first side of the cavity. The circuit board also includes a first plurality of conductive vias surrounding the cavity and the first plurality of vias include at least one blind via disposed adjacent to the first side of the cavity.

Abstract translation: 根据实施例，电路板包括信号线，该信号线包括第一导电层的至少一部分，第一导电层具有第一部分，该第一部分从空腔的第一侧延伸到电路板中的空腔上。 电路板还包括围绕空腔的第一多个导电通孔，并且第一多个通孔包括邻近空腔的第一侧设置的至少一个盲孔。

公开(公告)号：US09337522B2

公开(公告)日：2016-05-10

申请号：US14067640

申请日：2013-10-30

Applicant: Infineon Technologies AG

Inventor： Saverio Trotta ,  Jagjit Singh Bal ,  Maciej Wojnowski ,  Ernst Seler ,  Mehran Pour Mousavi

IPC: H01P5/107 ,  H01P3/12 ,  H04B10/2575 ,  H04B10/572 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01P5/107 ,  H01P3/12 ,  H04B10/2575 ,  H04B10/572 ,  H05K1/0206 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/181 ,  H05K3/4697

Abstract: According to an embodiment, a circuit board includes a signal line including at least portion of a first conductive layer that has a first portion extending over a cavity in the circuit board from a first side of the cavity. The circuit board also includes a first plurality of conductive vias surrounding the cavity and the first plurality of vias include at least one blind via disposed adjacent to the first side of the cavity.

Abstract translation: 根据实施例，电路板包括信号线，该信号线包括第一导电层的至少一部分，第一导电层具有第一部分，该第一部分从空腔的第一侧延伸到电路板中的空腔上。 电路板还包括围绕空腔的第一多个导电通孔，并且第一多个通孔包括邻近空腔的第一侧设置的至少一个盲孔。

公开(公告)号：US08952521B2

公开(公告)日：2015-02-10

申请号：US13736553

申请日：2013-01-08

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Walter Hartner ,  Ottmar Geitner ,  Gottfried Beer ,  Klaus Pressel ,  Mehran Pour Mousavi

IPC: H01L23/04 ,  H01L23/66 ,  H01L21/768 ,  H01L23/498 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17519 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01Q23/00 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01064 ,  H01L2924/01044 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract translation: 在本发明的一个实施例中，半导体封装包括具有第一主表面和相对的第二主表面的衬底。 芯片设置在基板中。 芯片包括在第一主表面处的多个接触垫。 第一天线结构设置在第一主表面处。 反射器设置在第二主表面处。