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    Vertical ferrite antenna including pre-fabricated connection members
    1.
    发明授权
    Vertical ferrite antenna including pre-fabricated connection members 有权

    公开(公告)号：US10651898B2

    公开(公告)日：2020-05-12

    申请号：US15184344

    申请日：2016-06-16

    Applicant: Infineon Technologies AG

    Inventor： Walther Pachler ,  Gottfried Beer ,  Juergen Hoelzl ,  Juergen Schilling ,  Harald Witschnig

    IPC: H01Q7/06 ,  H04B5/00

    Abstract: A ferrite antenna is disclosed. The ferrite antenna includes a ferrite core a first main face, a second main face opposite to the first main face, and side faces connecting the first and second main faces. A first plurality of conductor wires are disposed at the first main face of the ferrite core; a second plurality of conductor wires disposed at the second main face of the ferrite core. A first connection member is disposed at a first side face of the ferrite core, the first connection member including a first plurality of connection wires; and a second connection member is disposed at a second side face of the ferrite core, the second connection member including a second plurality of connection wires; wherein the first and second pluralities of conductor wires and the first and second plurality of connection wires are interconnected in such a way that they form an antenna coil, wherein the ferrite core is disposed in the interior space of the antenna coil.

    Semiconductor chip having a dense arrangement of contact terminals
    3.
    发明授权
    Semiconductor chip having a dense arrangement of contact terminals 有权

    公开(公告)号：US10090251B2

    公开(公告)日：2018-10-02

    申请号：US14808798

    申请日：2015-07-24

    Applicant: Infineon Technologies AG

    Inventor： Peter Ossimitz ,  Gottfried Beer ,  Juergen Hoegerl ,  Andreas Munding

    IPC: H01L23/538 ,  H01L23/00 ,  H01L21/66

    Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

    Semiconductor Device Having a Chip Under Package
    5.
    发明申请
    Semiconductor Device Having a Chip Under Package 有权
    具有芯片封装的半导体器件

    公开(公告)号：US20160225745A1

    公开(公告)日：2016-08-04

    申请号：US15012086

    申请日：2016-02-01

    Applicant: Infineon Technologies AG

    Inventor： Gottfried Beer ,  Peter Ossimitz

    IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/19104

    Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

    Abstract translation: 半导体器件封装包括电子元件和电互连。 电子部件附接到电互连。 电互连被配置为将电子部件电耦合到半导体器件封装的外部端子。 电互连具有面向电子部件的第一主面和与第一主面相对的第二主面。 半导体器件封装还包括面对电互连的第二主面的第一半导体芯片。

    On-Chip RF Shields with Backside Redistribution Lines
    9.
    发明申请
    On-Chip RF Shields with Backside Redistribution Lines 审中-公开
    带背面再分配线的片上RF屏蔽

    公开(公告)号：US20150024591A1

    公开(公告)日：2015-01-22

    申请号：US14505270

    申请日：2014-10-02

    Applicant: Infineon Technologies AG

    Inventor： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Heinrich Koerner

    IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6688 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2924/00014 ,  H01L2224/05552

    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

    Abstract translation: 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二 区域包括用于其他电路的装置。 该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

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