公开(公告)号：US20180082882A1

公开(公告)日：2018-03-22

申请号：US15701126

申请日：2017-09-11

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler ,  Thomas Christian Neidhart

IPC: H01L21/687 ,  G01R31/28 ,  B25B11/00

CPC classification number: H01L21/68785 ,  B25B11/005 ,  G01R31/2865 ,  G01R31/2874 ,  G01R31/2891 ,  H01L21/68757

Abstract: A wafer chuck configured to support a wafer during a wafer test procedure comprises a contact portion for supporting the wafer while being in contact with the wafer. The contact portion is made of a conductive material, the conductive material having a melting point larger than 1500° C.

公开(公告)号：US20160307858A1

公开(公告)日：2016-10-20

申请号：US15195434

申请日：2016-06-28

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Abstract translation: 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US09406572B2

公开(公告)日：2016-08-02

申请号：US14527811

申请日：2014-10-30

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler ,  Erich Griebl ,  Manfred Pirker ,  Andreas Moser

IPC: H01L21/66 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L22/14 ,  H01L21/28158 ,  H01L22/34 ,  H01L29/66568 ,  H01L29/94

Abstract: According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.

Abstract translation: 根据各种实施例，用于处理衬底的方法可以包括：在衬底上形成电介质层，电介质层可以包括多个测试区域; 在所述电介质层上形成导电层以接触所述多个测试区域中的介电层; 同时对多个测试区域中的电介质层进行电学检查，其中与多个测试区域中的电介质层接触的导电层的部分通过导电材料彼此导电连接; 以及将所述导电层分离成所述多个测试区域中与所述电介质层接触的所述导电层的部分。

公开(公告)号：US20140346509A1

公开(公告)日：2014-11-27

申请号：US13899906

申请日：2013-05-22

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Uwe Schmalzbauer ,  Rudolf Zelsacher

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L29/7391 ,  H01L29/7397 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.

Abstract translation: 第一实施例涉及半导体部件。 半导体部件具有半导体本体，其具有在垂直方向上与底侧隔开的底侧和顶侧。 在垂直方向上，半导体本体具有一定的厚度。 半导体部件还具有构造成检测半导体本体的裂纹的裂纹传感器。 裂纹传感器延伸到半导体体内。 裂纹传感器和底侧之间的距离小于半导体本体的厚度。

公开(公告)号：US20160254200A1

公开(公告)日：2016-09-01

申请号：US15149765

申请日：2016-05-09

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Uwe Schmalzbauer ,  Rudolf Zelsacher

IPC: H01L21/66 ,  H01L23/00 ,  H01L29/739

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L29/7391 ,  H01L29/7397 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor component includes a semiconductor body having a bottom side, a top side spaced distant from the bottom side in a vertical direction, and a thickness in the vertical direction, and a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body. A crack in the semiconductor body is detected by specifying a first value of a characteristic variable of the crack sensor, determining a second value of the characteristic variable of the crack sensor at a different time than the first value is specified, and determining the semiconductor body has a crack if the second value differs from the first value by more than a pre-defined difference.

Abstract translation: 半导体部件包括半导体本体，其具有底侧，与上下方向的底侧间隔开的顶面，以及垂直方向的厚度，以及构造为检测半导体本体的裂纹的裂纹传感器。 裂纹传感器延伸到半导体体内。 裂纹传感器和底侧之间的距离小于半导体本体的厚度。 通过指定裂纹传感器的特性变量的第一值，确定裂纹传感器的特性变量的第二值与指定第一值不同的时间来检测半导体本体中的裂纹，并且确定半导体本体 如果第二个值与第一个值的差异大于预定义的差异，则会产生破裂。

公开(公告)号：US09397055B2

公开(公告)日：2016-07-19

申请号：US14290448

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/82

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Abstract translation: 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US09343381B2

公开(公告)日：2016-05-17

申请号：US13899906

申请日：2013-05-22

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Uwe Schmalzbauer ,  Rudolf Zelsacher

IPC: H01L27/14 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L29/7391 ,  H01L29/7397 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.

Abstract translation: 第一实施例涉及半导体部件。 半导体部件具有半导体本体，其具有在垂直方向上与底侧隔开的底侧和顶侧。 在垂直方向上，半导体本体具有一定的厚度。 半导体部件还具有构造成检测半导体本体的裂纹的裂纹传感器。 裂纹传感器延伸到半导体体内。 裂纹传感器和底侧之间的距离小于半导体本体的厚度。

公开(公告)号：US10670972B2

公开(公告)日：2020-06-02

申请号：US14304665

申请日：2014-06-13

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler

IPC: G03B27/32 ,  G03F7/20

Abstract: A method for exposing a structure on a substrate includes positioning of an invariable reticle and a programmable reticle in a light path between a light source and a layer on a substrate to be exposed to light and exposing the layer on the substrate by light from the light source passing the invariable reticle and the programmable reticle.

公开(公告)号：US20150362841A1

公开(公告)日：2015-12-17

申请号：US14304665

申请日：2014-06-13

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler

IPC: G03F7/20

Abstract: A method for exposing a structure on a substrate includes positioning of an invariable reticle and a programmable reticle in a light path between a light source and a layer on a substrate to be exposed to light and exposing the layer on the substrate by light from the light source passing the invariable reticle and the programmable reticle.

Abstract translation: 用于在基板上曝光结构的方法包括将不变的掩模版和可编程掩模版定位在光源和基板上的层之间的光路中以暴露于光，并将来自光的光暴露在基板上的层 源通过不变的掩模版和可编程的掩模版。

公开(公告)号：US09673157B2

公开(公告)日：2017-06-06

申请号：US15195434

申请日：2016-06-28

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/82 ,  H01L21/683

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.