公开(公告)号：US20220010452A1

公开(公告)日：2022-01-13

申请号：US17482513

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chandrasekharan NAIR ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Srinivasan RAMAN ,  Roy DITTLER ,  Daniel SOWA ,  Robert BARESEL, II ,  Marcel WALL ,  Rahul MANEPALLI

IPC: C25D17/06 ,  C25D17/12 ,  C25D17/00 ,  H01L21/67

Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

公开(公告)号：US20240213328A1

公开(公告)日：2024-06-27

申请号：US18089494

申请日：2022-12-27

Applicant: INTEL CORPORATION

Inventor： Vinith BEJUGAM ,  Yonggang LI ,  Srinivas V. PIETAMBARAM ,  Chandrasekharan NAIR ,  Whitney BRYKS ,  Gene CORYELL

IPC: H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L29/1606 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/16 ,  H01L2924/15311

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.

公开(公告)号：US20240312942A1

公开(公告)日：2024-09-19

申请号：US18120904

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Vidya JAYARAM ,  Karan BHANGAONKAR ,  Chandrasekharan NAIR

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/19 ,  H01L21/31116 ,  H01L23/49816 ,  H01L23/5226 ,  H01L24/16 ,  H01L2224/16012 ,  H01L2224/19

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a layer with a film over the layer. In an embodiment, the film is an inorganic material. In an embodiment, the package substrate may further comprise a plurality of electrically conductive traces over the film, and a seed layer between the plurality of electrically conductive traces and the film. In an embodiment, edges of the seed layer are substantially aligned with edges of the plurality of electrically conductive traces.