公开(公告)号：US20220010452A1

公开(公告)日：2022-01-13

申请号：US17482513

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chandrasekharan NAIR ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Srinivasan RAMAN ,  Roy DITTLER ,  Daniel SOWA ,  Robert BARESEL, II ,  Marcel WALL ,  Rahul MANEPALLI

IPC: C25D17/06 ,  C25D17/12 ,  C25D17/00 ,  H01L21/67

Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

公开(公告)号：US20200245472A1

公开(公告)日：2020-07-30

申请号：US16637545

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Sandeep GAAN ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Ke LIU ,  Suddhasattwa NAD ,  Marcel A. WALL ,  Rahul N. MANEPALLI ,  Ravindra V. TANIKELLA

IPC: H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48 ,  C23C18/16 ,  C23C18/18 ,  C23C18/38

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20200328131A1

公开(公告)日：2020-10-15

申请号：US16380486

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Roy DITTLER ,  Jeremy ECTON ,  Darko GRUJICIC

IPC: H01L23/31 ,  H01L23/488

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20200251332A1

公开(公告)日：2020-08-06

申请号：US16269357

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Roy DITTLER ,  Darko GRUJICIC ,  Marcel WALL ,  Rahul MANEPALLI

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/285

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.