公开(公告)号：US11410264B2

公开(公告)日：2022-08-09

申请号：US16586855

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： James E. Akiyama ,  John Howard ,  Murali Ramadoss ,  Gary K. Smith ,  Todd M. Witter ,  Satish Ramanathan ,  Zhengmin Li

IPC: G09G5/36 ,  G06T1/20 ,  G09G5/14

Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.

公开(公告)号：US20220004351A1

公开(公告)日：2022-01-06

申请号：US17481572

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aswin Padmanabhan ,  Sangeeta Ghangam Manepalli ,  Kiran K. Velicheti ,  Robert James Johnston ,  Chandra Konduru ,  Todd M. Witter

IPC: G06F3/14 ,  H04N5/05

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

公开(公告)号：US12124759B2

公开(公告)日：2024-10-22

申请号：US17481572

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Aswin Padmanabhan ,  Sangeeta Ghangam Manepalli ,  Kiran K. Velicheti ,  Robert James Johnston ,  Chandra Konduru ,  Todd M. Witter

IPC: G06F3/14

CPC classification number: G06F3/1446

Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

公开(公告)号：US11935151B2

公开(公告)日：2024-03-19

申请号：US17859984

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： James E. Akiyama ,  John Howard ,  Murali Ramadoss ,  Gary K. Smith ,  Todd M. Witter ,  Satish Ramanathan ,  Zhengmin Li

IPC: G09G5/36 ,  G06T1/20 ,  G09G5/14

CPC classification number: G06T1/20 ,  G09G5/14 ,  G09G5/363 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/18

Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.

公开(公告)号：US20150113308A1

公开(公告)日：2015-04-23

申请号：US14578999

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： George R. Hayek ,  Todd M. Witter ,  Seh W. Kwa ,  Maximino Vasquez

IPC: G06F1/26 ,  G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3265 ,  G06F1/266 ,  G06F1/3218 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0659 ,  G09G5/006 ,  G09G5/395 ,  G09G2330/021 ,  G09G2360/18 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/14 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D50/20

Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.

Abstract translation: 描述技术来将命令传送到显示设备。 这些命令可以在辅助数据包的头字节字段中传输。 这些命令可用于使目标设备捕获帧，进入或退出自刷新模式或减少连接的电力使用。 此外，退出主链路待机模式的请求可能导致目标进入训练模式而不显式命令退出主链路待机模式。

公开(公告)号：US20210191878A1

公开(公告)日：2021-06-24

申请号：US16724804

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Ankur N. Shah ,  Geethacharan Rajagopalan ,  Ronald W. Silvas ,  Todd M. Witter

IPC: G06F12/1027 ,  G06F12/1009

Abstract: An apparatus to facilitate page translations is disclosed. The apparatus comprises a frame buffer to a plurality of pages of data, a plurality of display page tables to store virtual address to physical address translations to the pages of data in the frame buffer and a page table having a plurality of page table entries (PTEs), wherein each PTE maps to one of the plurality of display page tables.

公开(公告)号：US09870301B2

公开(公告)日：2018-01-16

申请号：US14231240

申请日：2014-03-31

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Eilon Hazan ,  Sean T. Baartmans ,  Marcus R. Winston ,  Rony Ghattas ,  Arie Bernstein ,  Todd M. Witter ,  Marcelo Yuffe

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/30 ,  G06F11/32 ,  G06F11/36

CPC classification number: G06F11/3476 ,  G06F11/3024 ,  G06F11/323 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3636 ,  G06F11/3656

Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.