公开(公告)号：US11239186B2

公开(公告)日：2022-02-01

申请号：US16334965

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Digvijay Raorane ,  Vijay K. Nair

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01Q1/22 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/13 ,  H01L25/065 ,  G06F1/18 ,  H01L23/48 ,  H01L23/522 ,  H01L23/552

Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include a substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed on the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

公开(公告)号：US20200098655A1

公开(公告)日：2020-03-26

申请号：US16619061

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay A. Raorane

IPC: H01L23/10 ,  H01L23/498 ,  H01L23/055 ,  H01L23/552 ,  H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

公开(公告)号：US10475750B2

公开(公告)日：2019-11-12

申请号：US16075513

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Pramod Malatkar

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/00 ,  H01L23/367 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L25/18

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed.

公开(公告)号：US10439671B2

公开(公告)日：2019-10-08

申请号：US15771865

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Vijay K. Nair

IPC: H04B1/44 ,  H01Q21/06 ,  H01Q3/42 ,  H01Q21/22 ,  H04B1/401 ,  H01Q3/36 ,  H01Q23/00

Abstract: Embodiments of the invention include a communication module that includes a die having a transceiver and a phase shifter die that is coupled to the die. The phase shifter includes a power combiner and splitter. The communication module also includes a substrate that is coupled to the phase shifter die. The substrate includes an antenna unit with steerable beam forming capability for transmitting and receiving communications.

公开(公告)号：US09991239B2

公开(公告)日：2018-06-05

申请号：US14767902

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Thorsten Meyer

IPC: H01L23/34 ,  H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/162 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/15331 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.

公开(公告)号：US11367708B2

公开(公告)日：2022-06-21

申请号：US16714502

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Georgios C. Dogiamis ,  Telesphor Kamgaing

IPC: H01L25/065 ,  H01L23/66 ,  H01L25/10 ,  H01L23/538 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01Q1/38

Abstract: Embodiments of the invention include a microelectronic device that includes a transceiver coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. An interposer substrate can provide a spacing between the first and second substrates.

公开(公告)号：US11335651B2

公开(公告)日：2022-05-17

申请号：US15773033

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Vijay K. Nair ,  Javier A. Falcon ,  Shawna M. Liff ,  Yoshihiro Tomita

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US11206008B2

公开(公告)日：2021-12-21

申请号：US16648115

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Feras Eid ,  Vijay K. Nair ,  Johanna M. Swan

IPC: H03H9/05 ,  H03H9/10 ,  H03H9/13 ,  H03H9/52 ,  H03H9/54

Abstract: Embodiments of the invention include an acoustic wave resonator (AWR) module. In an embodiment, the AWR module may include a first AWR substrate and a second AWR substrate affixed to the first AWR substrate. In an embodiment, the first AWR substrate and the second AWR substrate define a hermetically sealed cavity. A first AWR device may be positioned in the cavity and formed on the first AWR substrate, and a second AWR device may be positioned in the cavity and formed on the second AWR substrate. In an embodiment, a center frequency of the first AWR device is different than a center frequency of the second AWR device. In additional embodiment of the invention, the AWR module may be integrated into a hybrid filter. The hybrid filter may include an AWR module and other RF passive devices embedded in a packaging substrate.

公开(公告)号：US11189573B2

公开(公告)日：2021-11-30

申请号：US16069377

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay Raorane

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/78 ,  H01L23/498 ,  H01L21/82

Abstract: A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.

公开(公告)号：US11128029B2

公开(公告)日：2021-09-21

申请号：US16335535

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Digvijay Raorane

IPC: H01Q1/22 ,  H01L21/48 ,  H01L23/13 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01Q13/00

Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.