公开(公告)号：US08524528B2

公开(公告)日：2013-09-03

申请号：US13725574

申请日：2012-12-21

Applicant: Intermolecular Inc.

Inventor： Sean Barstow ,  Tony Chiang ,  Pragati Kumar ,  Sandra Malhotra

IPC: H01L21/00 ,  H01L21/16 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L45/1625 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

公开(公告)号：US08829647B2

公开(公告)日：2014-09-09

申请号：US13737156

申请日：2013-01-09

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Edward Haywood ,  Sandra Malhotra ,  Hiroyuki Ode

IPC: H01L29/92 ,  C23C16/455 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L29/92 ,  C23C16/45525 ,  H01L21/28562 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层含有使用高温低压ALD工艺形成的导电金属氧化物。 高温ALD工艺产生了具有增强的结晶度，较高密度，降低的收缩率和较低的碳污染的层。 高温ALD工艺可以用于底部电极和顶部电极层中的一个或两个。

公开(公告)号：US08679939B2

公开(公告)日：2014-03-25

申请号：US13737467

申请日：2013-01-09

Applicant: Intermolecular Inc.

Inventor： Sandra Malhotra ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L21/20

CPC classification number: H01L28/56 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

公开(公告)号：US08476141B2

公开(公告)日：2013-07-02

申请号：US13737785

申请日：2013-01-09

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/20 ,  H01L21/31

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130143384A1

公开(公告)日：2013-06-06

申请号：US13737785

申请日：2013-01-09

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US08652927B2

公开(公告)日：2014-02-18

申请号：US13738510

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L21/20

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

公开(公告)号：US20130140619A1

公开(公告)日：2013-06-06

申请号：US13738866

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

公开(公告)号：US09178010B2

公开(公告)日：2015-11-03

申请号：US13693901

申请日：2012-12-04

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Toshiyuki Hirota ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L21/02 ,  C23C16/455 ,  H01L29/423

CPC classification number: H01L28/60 ,  C23C16/45534 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L29/4234

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract translation: 一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层 电介质掺杂剂材料。 该方法还可用于在体电介质层和第二电极层之间形成阻挡层。 该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

公开(公告)号：US08901708B2

公开(公告)日：2014-12-02

申请号：US13675971

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobumichi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: H01L21/02 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

公开(公告)号：US20130119513A1

公开(公告)日：2013-05-16

申请号：US13693901

申请日：2012-12-04

Applicant: Intermolecular, Inc. ,  Elpida Memory , Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Toshiyuki Hirota ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/60 ,  C23C16/45534 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L29/4234

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract translation: 一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层 电介质掺杂剂材料。 该方法还可用于在体电介质层和第二电极层之间形成阻挡层。 该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。