公开(公告)号：US20240332239A1

公开(公告)日：2024-10-03

申请号：US18191950

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander Polomoff ,  Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Eric Perfecto ,  Katsuyuki Sakuma ,  SPYRIDON SKORDAS

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/80357 ,  H01L2224/95

Abstract: A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.

公开(公告)号：US20240170288A1

公开(公告)日：2024-05-23

申请号：US18056393

申请日：2022-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta Ghate Farooq ,  Qianwen Chen ,  Shahid Butt ,  Eric Perfecto ,  Michael P. Belyansky ,  Katsuyuki Sakuma ,  John Knickerbocker

IPC: H01L21/027 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/0275 ,  H01L23/5286 ,  H01L23/535

Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

公开(公告)号：US20240113055A1

公开(公告)日：2024-04-04

申请号：US17937429

申请日：2022-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Alexander Polomoff ,  Eric Perfecto ,  Katsuyuki Sakuma ,  Mukta Ghate Farooq ,  Spyridon Skordas ,  Sathyanarayanan Raghavan ,  Michael P. Belyansky

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03019 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06593 ,  H01L2924/3512

Abstract: A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.

公开(公告)号：US12300615B2

公开(公告)日：2025-05-13

申请号：US18056393

申请日：2022-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta Ghate Farooq ,  Qianwen Chen ,  Shahid Butt ,  Eric Perfecto ,  Michael P. Belyansky ,  Katsuyuki Sakuma ,  John Knickerbocker

IPC: H01L23/535 ,  B32B43/00 ,  H01L21/683 ,  H01L23/522 ,  H01L23/528

Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

公开(公告)号：US20230268275A1

公开(公告)日：2023-08-24

申请号：US17651883

申请日：2022-02-21

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  James J. Kelly ,  Eric Perfecto ,  SPYRIDON SKORDAS ,  Dale Curtis McHerron

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/5329 ,  H01L24/05 ,  H01L21/02118 ,  H01L2924/01029 ,  H01L2224/024

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.