公开(公告)号：US20240334616A1

公开(公告)日：2024-10-03

申请号：US18194597

申请日：2023-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keiji Matsumoto ,  Mukta Ghate Farooq ,  John Knickerbocker

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K7/20

CPC classification number: H05K3/4602 ,  H05K1/0212 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/0055 ,  H05K7/20509 ,  H05K2201/09145

Abstract: A method for manufacturing an electronic package includes etching one or more lateral surfaces of a PCB laminate to expose power and ground planes of the PCB laminate. A protective coating is applied to the exposed power and ground planes. At least one heat-generating component is affixed to a top surface of the PCB laminate. A heat spreader having a base section and flanged edges is formed and attached to the heat-generating components and the PCB laminate lateral surfaces, where the flanged edges of the heat spreader are thermally connected to the PCB laminate lateral surfaces. During operation of the heat-generating components, the flanged edges dissipate heat from the PCB laminate lateral surfaces.

公开(公告)号：US20240120705A1

公开(公告)日：2024-04-11

申请号：US17962434

申请日：2022-10-07

Applicant: International Business Machines Corporation

Inventor： Keiji Matsumoto ,  Mukta Ghate Farooq ,  John Knickerbocker

IPC: H01S5/024 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01S5/02469 ,  H01L23/367 ,  H01L23/373

Abstract: A heat spreader apparatus includes a first portion; a second portion; and a connecting portion between the first and second portions, with high-conductivity axes and a low-conductivity axis, the low-conductivity axis being directed between the first and second portions. In one or more embodiments, the first, second, and connecting portions are thermally anisotropic blocks, and the apparatus forms a rectangular prism.

公开(公告)号：US20240063171A1

公开(公告)日：2024-02-22

申请号：US18385373

申请日：2023-10-30

Applicant: International Business Machines Corporation

Inventor： Katsuyuki Sakuma ,  Mukta Ghate Farooq ,  Paul S. Andry ,  Russell Kastberg

IPC: H01L23/00 ,  H01L21/768 ,  B23K1/00

CPC classification number: H01L24/75 ,  H01L21/76895 ,  B23K1/0016 ,  H01L2224/81203

Abstract: An exemplary method includes at a bonding temperature, bonding a semiconductor chip to an organic laminate substrate using solder; without cooldown from the bonding temperature to room temperature, at an underfill dispense temperature, dispensing underfill between the semiconductor chip and the organic laminate substrate; and curing the underfill within a range of temperatures above the underfill dispense temperature. Another exemplary method includes depositing a first solder on pads of an organic laminate substrate; contacting a second solder on pillars of a semiconductor chip to the first solder on the pads of the organic laminate substrate; and solder bonding the semiconductor chip to the organic laminate substrate.

公开(公告)号：US20230352406A1

公开(公告)日：2023-11-02

申请号：US17661583

申请日：2022-05-02

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Liqiao Qin ,  Mukta Ghate Farooq ,  Ruilong Xie ,  Kisik Choi

IPC: H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5286 ,  H01L25/0657 ,  H01L24/33 ,  H01L24/48 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2224/48227 ,  H01L2224/04042 ,  H01L2224/73265

Abstract: An approach forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first wiring interconnect structure, and a third wiring interconnect structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.

公开(公告)号：US11791326B2

公开(公告)日：2023-10-17

申请号：US17315965

申请日：2021-05-10

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  Arvind Kumar ,  Ravi Nair

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/18 ,  H01L23/3675 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.

公开(公告)号：US20230197657A1

公开(公告)日：2023-06-22

申请号：US17555987

申请日：2021-12-20

Applicant: International Business Machines Corporation

Inventor： Katsuyuki Sakuma ,  Mukta Ghate Farooq

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/05 ,  H01L2224/16145 ,  H01L2224/1601 ,  H01L2224/1308 ,  H01L2224/13147 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13155 ,  H01L2224/81815 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor device and formation thereof. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a plurality of pillars interconnecting the first semiconductor structure and the second semiconductor structure. The plurality of pillars include a first solder layer and a second solder layer, wherein the first solder layer has a higher melting point than the second solder layer.

公开(公告)号：US20220262754A1

公开(公告)日：2022-08-18

申请号：US17178410

申请日：2021-02-18

Applicant: International Business Machines Corporation

Inventor： Katsuyuki Sakuma ,  Mukta Ghate Farooq

IPC: H01L23/00 ,  H01L23/488 ,  H01L21/48 ,  H01L23/532

Abstract: An approach to provide a method of joining a semiconductor chip to a semiconductor substrate, the approach includes depositing a nanoparticle paste and aligning each of one or more solder contacts on a semiconductor chip to a substrate bond pad. The approach includes sintering, in a reducing gaseous environment, the nanoparticle paste to connect the semiconductor chip to a semiconductor substrate bond pad.

公开(公告)号：US11171006B2

公开(公告)日：2021-11-09

申请号：US16703173

申请日：2019-12-04

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  James J. Kelly

IPC: H01L21/44 ,  H01L21/288 ,  H01L21/768 ,  C25D17/00 ,  C25D5/02 ,  C25D7/12 ,  H01L21/02

Abstract: Techniques for simultaneously plating features of varying sizes on a semiconductor substrate are provided. In one aspect, a method for electroplating includes: placing a shield over a wafer, offset from a surface of the wafer, which covers portions of the wafer and leaves other portions of the wafer uncovered; and depositing at least one metal onto the wafer by electroplating to simultaneously form metallurgical features of varying sizes on the wafer based on the shield altering local deposition rates for the portions of the wafer covered by the shield. An electroplating apparatus is also provided.

公开(公告)号：US20210175174A1

公开(公告)日：2021-06-10

申请号：US16703252

申请日：2019-12-04

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  Ravi K. Bonam ,  James J. Kelly ,  Spyridon Skordas

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.

公开(公告)号：US20240332239A1

公开(公告)日：2024-10-03

申请号：US18191950

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander Polomoff ,  Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Eric Perfecto ,  Katsuyuki Sakuma ,  SPYRIDON SKORDAS

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/80357 ,  H01L2224/95

Abstract: A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.