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    POWER REDUCTION IN VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS
    1.
    发明申请
    POWER REDUCTION IN VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS 有权

    公开(公告)号：US20220366110A1

    公开(公告)日：2022-11-17

    申请号：US17321708

    申请日：2021-05-17

    Applicant: International Business Machines Corporation

    Inventor： Lior Arie ,  Derrick Merrill Smith ,  Israel A. Wagner

    IPC: G06F30/327 ,  G01R31/26 ,  G06F30/337 ,  G06F30/398

    Abstract: In an approach utilizing static analysis, a processor receives a netlist for an integrated circuit. For at least one node of the integrated circuit in the netlist, a processor calculates (i) a total capacitive load of the respective node and (ii) a minimum required driver size. For a driver of the respective node, a processor (i) determines an effective driver size of the driver based on at least a number of fins of the driver and (ii) determines that the effective driver size exceeds the minimum required driver size multiplied by a predefined sizing margin. A processor, responsive to determining that the effective driver size exceeds the minimum required driver size multiplied by the predefined sizing margin, generates a report, where the report includes at least the driver and a suggestion to reduce the effective size of the driver.

    ADAPTIVE SRAM MEMORY CONTROL
    2.
    发明申请
    ADAPTIVE SRAM MEMORY CONTROL 有权

    公开(公告)号：US20220236905A1

    公开(公告)日：2022-07-28

    申请号：US17157609

    申请日：2021-01-25

    Applicant: International Business Machines Corporation

    Inventor： Israel A. Wagner ,  Yevgeniy Kuklin ,  Noam Jungmann

    IPC: G06F3/06

    Abstract: A method, system and product including adapting a value of a delay parameter that is utilized in an operation of a memory-cell array, wherein the delay parameter influences a ratio between an operation portion of a clock cycle and a pre-charge portion of the clock cycle, wherein writing or reading to the memory-cell array is enabled during the operation portion of the clock cycle and is disabled during the pre-charge portion of the clock cycle, wherein said adapting comprises: initializing the delay parameter with an initial value; writing a first test data into the memory-cell array; attempting to read from the memory-cell array a second test data; comparing the first test data with the second test data; and selecting a target value for the delay parameter based on said comparing.

    Area-efficient dynamic capacitor circuit for noise reduction in VLSI circuits
    5.
    发明授权
    Area-efficient dynamic capacitor circuit for noise reduction in VLSI circuits 有权

    公开(公告)号：US10756707B1

    公开(公告)日：2020-08-25

    申请号：US16419663

    申请日：2019-05-22

    Applicant: International Business Machines Corporation

    Inventor： Israel A. Wagner ,  Noam Jungmann ,  Elazar Kachir

    IPC: H03H11/12 ,  H01G4/00 ,  H01G4/40

    Abstract: A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

    Clock gating circuit for avoiding out-of-spec clock operations in self-timed circuits
    7.
    发明授权
    Clock gating circuit for avoiding out-of-spec clock operations in self-timed circuits 有权

    公开(公告)号：US12158771B2

    公开(公告)日：2024-12-03

    申请号：US18194337

    申请日：2023-03-31

    Applicant: International Business Machines Corporation

    Inventor： Israel A. Wagner ,  Hezi Shalom ,  Noam Jungmann ,  Elazar Kachir ,  Tomer Abraham Cohen

    IPC: G06F1/08 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/3237

    Abstract: A clock gating method and circuit for avoiding out-of-spec clock operations. The circuit comprises a clock gating section that gates a clock signal according to an enabling signal generated by an enabling signal controller, the enabling signal controller generating the enabling signal according to a set signal and a reset signal. The circuit further comprises a set signal generator that generates the set signal, a reset signal generator that generates the reset signal, and a feedback section that uses the enabling signal to generate the feedback signal for the reset signal generator. The reset signal generator generates the reset signal by using the feedback signal. The enabling signal controller further generates an acknowledgement signal having a high signal during a blocking period when the clock signal is blocked and utilizes the acknowledgement signal as an announcement to a higher circuit that the clock signal is blocked.

    Structure for static random access memory
    8.
    发明授权
    Structure for static random access memory 有权
    静态随机存取存储器的结构

    公开(公告)号：US09465905B1

    公开(公告)日：2016-10-11

    申请号：US14870112

    申请日：2015-09-30

    Applicant: International Business Machines Corporation

    Inventor： Lior Arie ,  Lidar Herooti ,  Noam Jungmann ,  Elazar Kachir ,  Hezi Shalom ,  Israel A. Wagner

    IPC: G11C11/00 ,  G06F17/50 ,  G11C16/10 ,  G11C7/18 ,  G11C11/413 ,  G11C16/08 ,  G11C11/412 ,  G11C11/419 ,  G11C16/04

    CPC classification number: G11C11/419 ,  G06F17/5077 ,  G06F17/5081 ,  G11C7/18 ,  G11C11/412 ,  G11C11/413 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

    Abstract: A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.

    Abstract translation: 这里描述了用于生成静态随机存取存储器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括生成耦合到第一组连续全局位线（GBL）和第一组局部位线（LBL）的第一局部评估逻辑的功能表示，所述第一局部评估逻辑包括多个设备。 该方法还包括通过设备生成通信地耦合到第一本地评估逻辑的第二本地评估逻辑的功能表示; 第二本地评估逻辑耦合到第二组连续GBL和第二组LBL。 另外，第二组连续的GBL连续到第一组连续GBL，第一和第二评估逻辑从LBL生成信号，使得一个GBL将在读或写周期中的任何一点处于活动状态 GBL不同时活动。

    Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability
    9.
    发明授权
    Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability 有权
    基于直接存储器的环形振荡器（DMRO），用于片上评估SRAM单元延迟和稳定性

    公开(公告)号：US09343182B2

    公开(公告)日：2016-05-17

    申请号：US13939008

    申请日：2013-07-10

    Applicant: International Business Machines Corporation

    Inventor： Noam Jungmann ,  Israel A. Wagner

    IPC: G11C29/50 ,  G11C29/12 ,  G11C11/41

    CPC classification number: G11C29/50012 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/1204

    Abstract: A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

    Abstract translation: 一种新颖有用的基于直接存储器的环形振荡器（DMRO）电路及相关方法，用于片上评估SRAM延迟和稳定性。 DMRO电路在振荡器的每个延迟级中使用未修改的SRAM单元。 添加少量外部电路以允许环振荡并检测读取不稳定性错误。 外部频率计数器是唯一需要的设备，因为无需获得精确的延迟测量并使用精确的波形发生器。 DMRO电路监控SRAM单元在其实际片上操作区域内的延迟和稳定性。 由电路提供的优点来自以下事实：测量环形振荡器的频率比测量信号的相位差或产生具有精确相位的信号产生更容易，并且将这样的信号传送到/从芯片传送。 此外，DMRO还可以监视读取稳定性故障。

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