公开(公告)号：US11168234B2

公开(公告)日：2021-11-09

申请号：US16750719

申请日：2020-01-23

Applicant: International Business Machines Corporation

Inventor： James L. Hedrick ,  Robert D. Miller ,  Deborah A. Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

IPC: C09J9/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  C09J11/04 ,  H01L25/00 ,  H01L25/065 ,  C09J183/04 ,  C09J179/08 ,  C09J179/04 ,  C09J11/06 ,  H01L23/60 ,  B82Y30/00 ,  B82Y40/00 ,  C08K5/544 ,  C08K5/548 ,  C08K5/5425 ,  C08K5/5465 ,  C08K7/24 ,  C08K3/04

Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

公开(公告)号：US20180340100A1

公开(公告)日：2018-11-29

申请号：US16004028

申请日：2018-06-08

Applicant: James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

IPC: C09J9/00 ,  H01L25/00 ,  C09J11/04 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/683 ,  C09J183/04 ,  C09J179/08 ,  C09J179/04 ,  C09J11/06 ,  H01L25/065 ,  C08K7/24 ,  C08K5/548 ,  C08K5/5465 ,  C08K5/544 ,  C08K5/5425 ,  B82Y40/00 ,  B82Y30/00 ,  C08K3/04

Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

公开(公告)号：US08963278B2

公开(公告)日：2015-02-24

申请号：US14088115

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Douglas C. La Tulipe, Jr. ,  Sampath Purushothaman ,  James Vichiconti

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/02 ,  H01L21/683 ,  H01L21/762 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/3065 ,  C23C16/402 ,  C23C16/513 ,  C23C16/56 ,  H01L21/02002 ,  H01L21/187 ,  H01L21/3221 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/77 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/06 ,  H01L2221/68377 ,  H01L2224/83121 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Abstract translation: 含有集成半导体器件的施主晶片。 施主晶片具有具有器件层和掩埋绝缘层的施主晶片膜部分。 施主晶片膜部分具有多个集成半导体器件，其中多个半导体器件内的每个集成半导体器件对应于在施主晶片上形成的管芯。 供体晶片膜部分的直径至少为200mm。 施主晶片具有从施主晶片膜部分的区域基本上去除的结晶衬底，使得该区域中的施主晶片膜的器件层和掩埋绝缘层被配置为符合受体上的图案特定拓扑 表面。 施主晶片还具有附接到施主晶片的在施主晶片膜部分外部的区域的支撑结构。

公开(公告)号：US10777454B2

公开(公告)日：2020-09-15

申请号：US16030163

申请日：2018-07-09

Applicant: International Business Machines Corporation

Inventor： Sampath Purushothaman ,  Roy Rongqing Yu

IPC: H01L21/768 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00 ,  H01L25/065 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/84 ,  H01L23/544 ,  H01L25/00 ,  H01L29/06 ,  H01L23/522

Abstract: An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.

公开(公告)号：US10651086B2

公开(公告)日：2020-05-12

申请号：US16118243

申请日：2018-08-30

Applicant: International Business Machines Corporation

Inventor： Sampath Purushothaman ,  Roy Rongqing Yu

IPC: H01L21/768 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00 ,  H01L25/065 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/84 ,  H01L23/544 ,  H01L25/00 ,  H01L29/06 ,  H01L23/522

Abstract: A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.

公开(公告)号：US20180138084A1

公开(公告)日：2018-05-17

申请号：US15863675

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： James P. Doyle ,  Geraud Dubois ,  Nicholas C. Fuller ,  Teddie P. Magbitang ,  Robert D. Miller ,  Sampath Purushothaman ,  Will Volksen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295

Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.

公开(公告)号：US08927087B2

公开(公告)日：2015-01-06

申请号：US14028974

申请日：2013-09-17

Applicant: International Business Machines Corporation

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

IPC: B32B3/00 ,  B32B15/04 ,  B23K20/24 ,  H01L23/00 ,  B23K20/233 ,  B23K20/02

CPC classification number: H01L24/05 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K2101/42 ,  H01L24/03 ,  H01L24/08 ,  H01L24/12 ,  H01L24/80 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24545 ,  Y10T428/24612 ,  Y10T428/31678 ,  H01L2924/00012 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.

Abstract translation: 公开了包括金属电介质图案在表面上与在电介质上方凸起的金属以及相关结构的接合。 一种结构包括：在其表面上具有金属 - 电介质图案的第一基板，所述金属 - 电介质图案包括：具有凹的上表面的金属; 以及具有基本上均匀的上表面的电介质，其中所述第一衬底上的金属在所述第一衬底上的电介质上方升高; 以及与所述第一基板接合的第二基板，所述第二基板包括：电介质; 以及大体位于所述第二基板的电介质下方的金属，其中所述第一基板和所述第二基板仅在所述金属处与所述第一基板接合，所述金属与所述第二基板接合。

公开(公告)号：US10796958B2

公开(公告)日：2020-10-06

申请号：US16034249

申请日：2018-07-12

Applicant: International Business Machines Corporation

Inventor： Sampath Purushothaman ,  Roy Rongqing Yu

IPC: H01L21/768 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00 ,  H01L25/065 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/84 ,  H01L23/544 ,  H01L25/00 ,  H01L29/06 ,  H01L23/522

Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

公开(公告)号：US10767084B2

公开(公告)日：2020-09-08

申请号：US16004028

申请日：2018-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

Inventor： James L. Hedrick ,  Robert Dennis Miller ,  Deborah Ann Neumayer ,  Sampath Purushothaman ,  Mary E. Rothwell ,  Willi Volksen ,  Roy R. Yu

IPC: C09J9/00 ,  B32B17/00 ,  C09J179/08 ,  C09J11/04 ,  H01L23/16 ,  B32B33/00 ,  C09J11/06 ,  C09J179/04 ,  C09J183/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/60 ,  H01L23/48 ,  B82Y30/00 ,  B82Y40/00 ,  C08K5/544 ,  C08K5/548 ,  C08K5/5425 ,  C08K5/5465 ,  C08K7/24 ,  C08K3/04

Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

公开(公告)号：US10340182B2

公开(公告)日：2019-07-02

申请号：US14953466

申请日：2015-11-30

Applicant: International Business Machines Corporation

Inventor： James P. Doyle ,  Geraud Dubois ,  Nicholas C. Fuller ,  Teddie P. Magbitang ,  Robert D. Miller ,  Sampath Purushothaman ,  Willi Volksen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.