中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.017 seconds)

    LARGE AREA CONTACTS FOR SMALL TRANSISTORS
    1.
    发明申请
    LARGE AREA CONTACTS FOR SMALL TRANSISTORS 审中-公开
    小型晶体管的大面积接触

    公开(公告)号：US20170012130A1

    公开(公告)日：2017-01-12

    申请号：US15273778

    申请日：2016-09-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

    Inventor： Xiuyu CAI ,  Qing LIU ,  Ruilong XIE ,  Chun-Chen YEH

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L21/8234

    Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

    Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

    HETERO-CHANNEL FINFET
    2.
    发明申请
    HETERO-CHANNEL FINFET 有权

    公开(公告)号：US20160190317A1

    公开(公告)日：2016-06-30

    申请号：US14587655

    申请日：2014-12-31

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing LIU ,  Ruilong XIE ,  Chun-chen YEH ,  Xiuyu CAI

    IPC: H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417

    CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7851

    Abstract: A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.

    Abstract translation: 异构沟道FinFET器件在具有硅沟道的FinFET器件上提供增强的开关性能，并且比具有锗通道的FinFET器件更容易集成到制造工艺中。 具有异质Si / SiGe沟道的FinFET器件包括具有由硅构成的中心区域和由SiGe制成的侧壁区域的翅片。 异质沟道pFET器件特别地具有比硅器件或SiGe器件更高的载流子迁移率和更小的栅极引起漏极漏电流。 异质沟道FinFET允许沟道的SiGe部分的Ge浓度在约25-40％的范围内，并且允许翅片高度超过40nm，同时保持稳定。

    FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION
    3.
    发明申请
    FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION 有权
    提高门高度均匀性和层间电介质保护

    公开(公告)号：US20140110794A1

    公开(公告)日：2014-04-24

    申请号：US13654717

    申请日：2012-10-18

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

    Inventor： Ruilong XIE ,  Xiuyu CAI ,  Pranatharthiharan BALASUBRAMANIAN ,  Shom PONOTH

    IPC: H01L21/283 ,  H01L29/423

    CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

    Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

    Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

    METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH ISOLATION PILLARS BETWEEN ADJACENT SEMICONDUCTOR FINS
    6.
    发明申请
    METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH ISOLATION PILLARS BETWEEN ADJACENT SEMICONDUCTOR FINS 有权
    用于制造具有相邻半导体器件之间的隔离支架的半导体器件的方法

    公开(公告)号：US20150357439A1

    公开(公告)日：2015-12-10

    申请号：US14295618

    申请日：2014-06-04

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

    Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

    Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

    REDUCED TRENCH PROFILE FOR A GATE
    7.
    发明申请
    REDUCED TRENCH PROFILE FOR A GATE 有权
    减少一个门口的情况

    公开(公告)号：US20160181384A1

    公开(公告)日：2016-06-23

    申请号：US14581741

    申请日：2014-12-23

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen YEH

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

    CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

    Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

    Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

    CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD
    8.
    发明申请
    CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD 审中-公开
    具有低电阻接触和制造方法的CMOS结构

    公开(公告)号：US20150243660A1

    公开(公告)日：2015-08-27

    申请号：US14189509

    申请日：2014-02-25

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

    IPC: H01L27/092 ,  H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L21/8238

    Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

    Abstract translation: 一种制造CMOS集成电路结构的方法和CMOS集成电路结构。 该方法包括产生一个或多个n型阱，产生一个或多个p型阱，产生嵌入在一个或多个n型阱中的每一个中的一个或多个pFET源极漏极，产生一个或多个nFET源极漏极 嵌入在所述一个或多个p型阱中的每一个中，产生覆盖所述一个或多个pFET源极漏极中的每一个的pFET触点，以及产生覆盖所述一个或多个nFET源极漏极中的每一个的nFET触点。 一个或多个pFET源极漏极中的每一个的材料包括掺杂有p型材料的硅; 一个或多个nFET源极漏极中的每一个的材料包括掺杂有n型材料的硅; 每个pFET触点的材料包括硅化镍; 并且每个nFET接触的材料包括硅化钛。

Patent Agency Ranking