公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US07312143B2

公开(公告)日：2007-12-25

申请号：US11717691

申请日：2007-03-14

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

摘要翻译： 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20060214293A1

公开(公告)日：2006-09-28

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

摘要翻译： 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20070176290A1

公开(公告)日：2007-08-02

申请号：US11717691

申请日：2007-03-14

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20060118972A1

公开(公告)日：2006-06-08

申请号：US11339973

申请日：2006-01-26

申请人： Seung-Duk Baek ,  In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

发明人： Seung-Duk Baek ,  In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

摘要： Packaged integrated circuit devices include a package substrate and a multi-chip stack of integrated circuit devices on the package substrate. The multi-chip stack includes at least one chip-select rerouting conductor. This rerouting conductor extends from the package substrate to a chip pad on an upper one of the chips in the multi-chip stack. The chip-select rerouting conductor extends through a first via hole in a lower one of the chips in the multi-chip stack.

公开(公告)号：US20060019467A1

公开(公告)日：2006-01-26

申请号：US11147677

申请日：2005-06-08

申请人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

发明人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Young-Hee Song ,  Myeong-Soon Park

IPC分类号： H01L21/78

CPC分类号： H01L23/481 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

摘要： Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.

摘要翻译： 形成集成电路芯片的方法包括在其上具有多个接触焊盘的半导体晶片中形成多个交叉交叉的沟槽，并用电绝缘层填充交叉沟槽。 然后对电绝缘层进行图案化以在其中限定至少第一和第二通孔，该第一和第二通孔在第一个十字交叉的树丛中延伸。 然后分别用第一和第二贯通芯片连接电极填充第一和第二通孔。 然后通过与交叉交叉的沟槽的位置重叠的交叉图案切割电绝缘层，将半导体晶片切割成多个集成电路芯片。

公开(公告)号：US20070069320A1

公开(公告)日：2007-03-29

申请号：US11486041

申请日：2006-07-14

申请人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

发明人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

IPC分类号： H01L31/00

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/114 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/013

摘要： A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.

摘要翻译： 布线结构可以包括垫，导电图案和绝缘光致抗蚀剂结构。 垫可以设置在主体上并电连接到主体的电路单元。 导电图案可以设置在主体上并且可以电连接到垫。 绝缘光致抗蚀剂结构可以设置在导电图案的表面上。 绝缘光致抗蚀剂结构可以具有接触孔，导电图案可以通过该接触孔部分地暴露。 绝缘光致抗蚀剂结构可以通过在导电层上提供感光性光致抗蚀剂膜，并通过两个照相工艺对感光性光刻胶膜进行图案化来制造。

公开(公告)号：US07545027B2

公开(公告)日：2009-06-09

申请号：US11448772

申请日：2006-06-08

申请人： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

发明人： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

摘要： A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

摘要翻译： 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US20070108573A1

公开(公告)日：2007-05-17

申请号：US11448772

申请日：2006-06-08

申请人： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

发明人： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

摘要： A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

摘要翻译： 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US20070170556A1

公开(公告)日：2007-07-26

申请号：US11635011

申请日：2006-12-07

申请人： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  In-Young Lee ,  Dong-Ho Lee

发明人： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  In-Young Lee ,  Dong-Ho Lee

IPC分类号： H01L23/495

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/062 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/09745 ,  H05K2203/1184 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.

摘要翻译： 半导体器件可以包括半导体元件。 可以在半导体元件上提供一层材料，该层可以具有可以暴露接合焊盘的开口。 可以在第一接合焊盘上提供至少一个凸缘结构，所述至少一个凸缘结构由具有不同蚀刻速率的至少两个金属层制成。