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    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME 审中-公开
    封装基板及其制造方法

    公开(公告)号：US20140084413A1

    公开(公告)日：2014-03-27

    申请号：US13965842

    申请日：2013-08-13

    Applicant: UNIMICRON TECHNOLOGY CORPORATION ,  INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Yu-Hua CHEN ,  Wei-Chung LO ,  Dyi-Chung HU ,  Chang-Hong HSIEH

    IPC: H01L23/522

    CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/04 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced.

    Abstract translation: 提供封装基板和制造封装基板的方法。 封装衬底包括具有顶表面和与顶表面相对的底表面的衬底; 形成在所述基板的上表面上的绝缘保护层; 嵌入并从绝缘保护层暴露的插入体; 以及提供在或插入到插入器中的被动元件。 通过将无源部件集成到封装基板中，当在插入件上设置芯片时，可以缩短芯片和无源部件之间的导电路径，并且芯片的引脚具有稳定的电压。 因此，整体电气性能得到提高。

    PACKAGE SUBSTRATE AND METHOD OF FORMING THE SAME
    3.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FORMING THE SAME 审中-公开
    封装基板及其形成方法

    公开(公告)号：US20140117557A1

    公开(公告)日：2014-05-01

    申请号：US13966045

    申请日：2013-08-13

    Applicant: UNIMICRON TECHNOLOGY CORPORATION ,  INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Yu-Hua CHEN ,  Wei-Chung LO ,  Dyi-Chung HU ,  Chang-Hong HSIEH

    IPC: H01L23/48 ,  H01L21/56

    CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

    Abstract: A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased.

    Abstract translation: 公开了封装基板和形成封装基板的方法。 封装衬底包括具有多个导电通孔的插入件和形成在导电通孔的侧壁上的第一绝缘层，形成在插入件一侧上的第二绝缘层和形成在第二绝缘层中的多个导电通孔 绝缘层并电连接到导电通孔。 通过增加第一绝缘层的厚度，可以减小导电通孔的面直径，从而可以增加插入件中的导电通孔的布局密度。

    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
    封装基板及其制造方法

    公开(公告)号：US20140102777A1

    公开(公告)日：2014-04-17

    申请号：US14010250

    申请日：2013-08-26

    Applicant: Unimicron Technology Corporation ,  Industrial Technology Research Institute

    Inventor： Yu-Hua CHEN ,  Wei-Chung LO ,  Dyi-Chung HU ,  Chang-Hong HSIEH

    IPC: H05K3/40 ,  H05K1/11

    CPC classification number: H05K3/4038 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/115 ,  Y10T29/49165

    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.

    Abstract translation: 提供封装基板和制造封装基板的方法。 封装衬底可以包括具有至少一个导电通孔，形成在插入器的一侧上的光敏电介质层和至少一个形成在光敏电介质层中的导电通孔并且与导电通孔 通过。 通过具有高对准精度的光刻工艺，可以在感光介电层上形成至少一个具有极小直径的通孔，并与导电通孔对齐。 因此，导电通孔可以根据需要减小其直径，而不考虑与至少一个通孔的对准。 因此，插入件上的导电贯通孔的互连密度增加。

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