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公开(公告)号：US10680605B2
公开(公告)日：2020-06-09
申请号：US15908087
申请日：2018-02-28
Applicant: Infineon Technologies AG
Inventor： Bernd Schleicher , Ruediger Bauder , Daniel Kehrer , Valentyn Solomko
IPC: H03K17/693 , H03K17/687 , H01P1/15 , H03K17/10 , H04B1/40
Abstract: An RF switch includes series-coupled RF switch cells coupled between an RF input and ground, each RF switch cell having an input, and a biasing network having outputs for individually biasing each of the RF switch cell inputs to a distinct bias voltage based upon a rank number of the RF switch cell.
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公开(公告)号：US09866260B2
公开(公告)日：2018-01-09
申请号：US14834208
申请日：2015-08-24
Applicant: Infineon Technologies AG
Inventor： Nikolay Ilkov , Daniel Kehrer , Valentyn Solomko
CPC classification number: H04B1/44 , H03H7/48 , H04B1/0458
Abstract: In accordance with an embodiment, a circuit includes a first directional coupler comprising a first input port, a first transmitted port, a first isolated port and a first coupled port, where the first directional coupler disposed on a first substrate. The circuit also includes a first direction select switch having a first switch input port coupled to the first isolated port, a second switch input port coupled to the first coupled port, and a first switch output port, where the first direction select switch is disposed on the first substrate along with the directional coupler.
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公开(公告)号：US20160079649A1
公开(公告)日：2016-03-17
申请号：US14834208
申请日：2015-08-24
Applicant: Infineon Technologies AG
Inventor： Nikolay Ilkov , Daniel Kehrer , Valentyn Solomko
CPC classification number: H04B1/44 , H03H7/48 , H04B1/0458
Abstract: In accordance with an embodiment, a circuit includes a first directional coupler comprising a first input port, a first transmitted port, a first isolated port and a first coupled port, where the first directional coupler disposed on a first substrate. The circuit also includes a first direction select switch having a first switch input port coupled to the first isolated port, a second switch input port coupled to the first coupled port, and a first switch output port, where the first direction select switch is disposed on the first substrate along with the directional coupler.
Abstract translation: 根据实施例，电路包括第一定向耦合器，其包括第一输入端口，第一传输端口，第一隔离端口和第一耦合端口，其中第一定向耦合器设置在第一基板上。 电路还包括第一方向选择开关，其具有耦合到第一隔离端口的第一开关输入端口，耦合到第一耦合端口的第二开关输入端口和第一开关输出端口，其中第一方向选择开关设置在 第一衬底以及定向耦合器。
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公开(公告)号：US20190267990A1
公开(公告)日：2019-08-29
申请号：US15908087
申请日：2018-02-28
Applicant: Infineon Technologies AG
Inventor： Bernd Schleicher , Ruediger Bauder , Daniel Kehrer , Valentyn Solomko
IPC: H03K17/687 , H03K17/10 , H03K17/693 , H01P1/15 , H04B1/40
Abstract: An RF switch includes series-coupled RF switch cells coupled between an RF input and ground, each RF switch cell having an input, and a biasing network having outputs for individually biasing each of the RF switch cell inputs to a distinct bias voltage based upon a rank number of the RF switch cell
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公开(公告)号：US09742364B2
公开(公告)日：2017-08-22
申请号：US15144907
申请日：2016-05-03
Applicant: Infineon Technologies AG
Inventor： Nikolay Ilkov , Paulo Oliveira , Daniel Kehrer
CPC classification number: H03F3/19 , H03F1/0261 , H03F3/191 , H03F2200/111 , H03F2200/249 , H03F2200/294 , H03F2200/39 , H03F2200/451 , H04B1/10
Abstract: In accordance with an embodiment, a circuit includes a low noise amplifier transistor disposed on a first integrated circuit, a single pole multi throw (SPMT) switch disposed on a second integrated circuit, and a bypass switch coupled between a control node of the low noise amplifier transistor and an output node of the low noise amplifier transistor. The SPMT switch couples a plurality of module input terminals to a control node of the low noise amplifier transistor, and the bypass switch including a first switch coupled between the control node of the low noise amplifier transistor and an intermediate node, a second switch coupled between the intermediate node and the output node of the low noise amplifier transistor, and a third switch coupled between the intermediate node and a first reference node. The first integrated circuit and the second integrated circuit are disposed on a substrate.
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Patent Agency Ranking
公开(公告)号：US09479126B2
公开(公告)日：2016-10-25
申请号：US14462793
申请日：2014-08-19
Applicant: Infineon Technologies AG
Inventor： Nikolay Ilkov , Paulo Oliveira , Winfried Bakalski , Daniel Kehrer
CPC classification number: H03F1/565 , H03F1/0205 , H03F3/19 , H03F2200/213 , H03F2200/222 , H03F2200/252 , H03F2200/294 , H03F2200/421 , H03F2200/451
Abstract: In accordance with an embodiment, a circuit includes a first signal path coupled between an input port and an output port, and a second coupled between the input port and the output port in parallel with the first signal path. The first signal path includes a low noise amplifier (LNA) having an input node coupled to the input port, and the second signal path includes a switch coupled between the input port and the output port.
Abstract translation: 根据实施例，电路包括耦合在输入端口和输出端口之间的第一信号路径，以及耦合在输入端口和输出端口之间并与第一信号路径连接的第二信号路径。 第一信号路径包括具有耦合到输入端口的输入节点的低噪声放大器（LNA），并且第二信号路径包括耦合在输入端口和输出端口之间的开关。
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公开(公告)号：US20150280654A1
公开(公告)日：2015-10-01
申请号：US14227479
申请日：2014-03-27
Applicant: Infineon Technologies AG
Inventor： Daniel Kehrer , Paulo Oliveira , Thomas Leitner
CPC classification number: H03F1/26 , H03F1/565 , H03F3/19 , H03F3/193 , H03F3/211 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/391 , H03F2200/451 , H03F2203/21109 , H03F2203/21112 , H03F2203/21136 , H04B1/006 , H04B1/10 , H04B1/18
Abstract: An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.
Abstract translation: 本文描述的实施例包括包括多个单独的输入端子，多个晶体管的低噪声放大器（LNA）以及耦合到第一参考端子和LNA的单个输出端的输出网络。 每个晶体管包括耦合到所述多个分离的输入端之一的导通路径和控制端。 输出网络也耦合到多个晶体管中的每一个的导通路径。
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公开(公告)号：US20150261708A1
公开(公告)日：2015-09-17
申请号：US14213173
申请日：2014-03-14
Applicant: Infineon Technologies AG
Inventor： Daniel Kehrer
IPC: G06F13/40 , G06F13/364
CPC classification number: G06F13/4022 , H04B1/005
Abstract: In accordance with an embodiment of the present invention, a chip set for a mobile device includes a slave device chip and an interface circuit chip that includes a slave bus interface for controlling the slave device chip through an analog bus. The slave bus interface is coupled to a master bus interface via a digital bus of the mobile device. The slave bus interface is configured to be driven by the master bus interface.
Abstract translation: 根据本发明的实施例，用于移动设备的芯片组包括从设备芯片和接口电路芯片，该接口电路芯片包括用于通过模拟总线控制从设备芯片的从总线接口。 从总线接口经由移动设备的数字总线耦合到主总线接口。 从总线接口被配置为由主总线接口驱动。
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公开(公告)号：US09866177B2
公开(公告)日：2018-01-09
申请号：US15130488
申请日：2016-04-15
Applicant: Infineon Technologies AG
Inventor： Daniel Kehrer , Paulo Oliveira , Thomas Leitner
CPC classification number: H03F1/26 , H03F1/565 , H03F3/19 , H03F3/193 , H03F3/211 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/391 , H03F2200/451 , H03F2203/21109 , H03F2203/21112 , H03F2203/21136 , H04B1/006 , H04B1/10 , H04B1/18
Abstract: An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.
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公开(公告)号：US09711462B2
公开(公告)日：2017-07-18
申请号：US13889370
申请日：2013-05-08
Applicant: Infineon Technologies AG
Inventor： Gottfried Beer , Dominic Maier , Ulrich Wachter , Daniel Kehrer
IPC: H01L23/552 , H01L21/56 , H01L21/58 , H01L21/60 , H01L23/52 , H01L25/065 , H01L23/31 , H01L23/00
CPC classification number: H01L23/552 , H01L21/56 , H01L23/3121 , H01L23/3128 , H01L24/18 , H01L24/19 , H01L24/20 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/00
Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.
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