公开(公告)号：US09324642B2

公开(公告)日：2016-04-26

申请号：US14077582

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Frank Püschner ,  Bernhard Schätzler ,  Teck Sim Lee ,  Franz Gabler ,  Pei Pei Kong ,  Boon Huat Lim

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames.

Abstract translation: 引线框架条包括多个连接的单元引线框架，每个单元引线框架具有管芯焊盘和连接到单元引线框架的外围的多个引线。 将半导体管芯附接到管芯片。 模制化合物覆盖包括半导体管芯的单元引线框架。 在引线框架条的测试或其它处理之前，间隙被蚀刻到由相邻单元引线框架共享的引线的区域中。 差距至少主要通过共享潜在客户。 在随后的处理之前，在包括在共享引线之间的间隙的下方的单元引线框的周围的模塑料中部分地切割，以使单元引线框架的引线电隔离。

公开(公告)号：US20150130037A1

公开(公告)日：2015-05-14

申请号：US14077582

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Frank Püschner ,  Bernhard Schätzler ,  Teck Sim Lee ,  Franz Gabler ,  Pei Pei Kong ,  Boon Huat Lim

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/66

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames.

Abstract translation: 引线框架条包括多个连接的单元引线框架，每个单元引线框架具有管芯焊盘和连接到单元引线框架的外围的多个引线。 将半导体管芯附接到管芯片。 模制化合物覆盖包括半导体管芯的单元引线框架。 在引线框架条的测试或其它处理之前，间隙被蚀刻到由相邻单元引线框架共享的引线的区域中。 差距至少主要通过共享潜在客户。 在随后的处理之前，在包括在共享引线之间的间隙的下方的单元引线框的周围的模塑料中进行部分切割以使单元引线框架的引线电隔离。

公开(公告)号：US10519030B2

公开(公告)日：2019-12-31

申请号：US15478946

申请日：2017-04-04

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Franz Gabler ,  Thomas Mueller ,  Horst Theuss ,  Mathias Vaupel

IPC: B81B7/00 ,  B81C1/00

Abstract: A package which comprises a carrier, a transducer mounted on the carrier and configured for converting between a package-external property and an electric signal, a package housing at least partially housing at least one of the carrier and the transducer, and a sealing which forms at least part of the package housing for sealing between the package and a package-external body.

公开(公告)号：US20160042998A1

公开(公告)日：2016-02-11

申请号：US14453639

申请日：2014-08-07

Applicant: Infineon Technologies AG

Inventor： Frank Pueschner ,  Bernhard Schaetzler ,  Franz Gabler

IPC: H01L21/82 ,  H01L21/302 ,  H01L21/56

CPC classification number: H01L21/82 ,  H01L21/302 ,  H01L21/561 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to various embodiments, a method of processing a substrate may include: forming a plurality of trenches into a substrate between two chip structures in the substrate, the trenches defining at least one pillar between the two chip structures and a sidewall on each of said two chip structures; disposing an auxiliary carrier on the substrate to hold the chip structures and the at least one pillar; at least partially filling the trenches with encapsulation material to cover the at least one pillar and the sidewalls, thereby at least partially encapsulating the chip structures; removing a portion of the encapsulation material to expose at least a portion of the at least one pillar; and at least partially removing the at least one pillar.

Abstract translation: 根据各种实施例，处理衬底的方法可以包括：在衬底中的两个芯片结构之间形成多个沟槽到衬底中，所述沟槽限定两个芯片结构之间的至少一个柱和在所述两个芯片结构中的每一个上的侧壁 芯片结构; 在所述基板上设置辅助载体以保持所述芯片结构和所述至少一个支柱; 至少部分地用封装材料填充沟槽以覆盖所述至少一个柱和侧壁，从而至少部分地封装所述芯片结构; 去除所述封装材料的一部分以暴露所述至少一个支柱的至少一部分; 并且至少部分地去除所述至少一个支柱。

公开(公告)号：US09780061B2

公开(公告)日：2017-10-03

申请号：US14287080

申请日：2014-05-26

Applicant: Infineon Technologies AG

Inventor： Franz Gabler ,  Horst Theuss

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8392 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer at least on portions of the electronic chip; and molding an encapsulation which covers the electronic chip and the supporting structure at least partially by using a molding material comprising a matrix material and a conductive filler material.

公开(公告)号：US09548248B2

公开(公告)日：2017-01-17

申请号：US14453639

申请日：2014-08-07

Applicant: Infineon Technologies AG

Inventor： Frank Pueschner ,  Bernhard Schaetzler ,  Franz Gabler

IPC: H01L21/82 ,  H01L21/302 ,  H01L21/304 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/82 ,  H01L21/302 ,  H01L21/561 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to various embodiments, a method of processing a substrate may include: forming a plurality of trenches into a substrate between two chip structures in the substrate, the trenches defining at least one pillar between the two chip structures and a sidewall on each of said two chip structures; disposing an auxiliary carrier on the substrate to hold the chip structures and the at least one pillar; at least partially filling the trenches with encapsulation material to cover the at least one pillar and the sidewalls, thereby at least partially encapsulating the chip structures; removing a portion of the encapsulation material to expose at least a portion of the at least one pillar; and at least partially removing the at least one pillar.

Abstract translation: 根据各种实施例，处理衬底的方法可以包括：在衬底中的两个芯片结构之间形成多个沟槽到衬底中，所述沟槽限定两个芯片结构之间的至少一个柱和在所述两个芯片结构中的每一个上的侧壁 芯片结构; 在所述基板上设置辅助载体以保持所述芯片结构和所述至少一个支柱; 至少部分地用封装材料填充沟槽以覆盖所述至少一个柱和侧壁，从而至少部分地封装所述芯片结构; 去除所述封装材料的一部分以暴露所述至少一个支柱的至少一部分; 并且至少部分地去除所述至少一个支柱。