公开(公告)号：US20180102302A1

公开(公告)日：2018-04-12

申请号：US15730758

申请日：2017-10-12

Applicant: Infineon Technologies AG

Inventor： Andreas GRASSMANN ,  Wolfram HABLE ,  Juergen HOEGERL ,  Angela KESSLER ,  Ivan NIKITIN ,  Achim STRASS

IPC: H01L23/373 ,  H01L23/492 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/3735 ,  H01L23/4334 ,  H01L23/4924 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45014 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/206

Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.

公开(公告)号：US20180096919A1

公开(公告)日：2018-04-05

申请号：US15723431

申请日：2017-10-03

Applicant: Infineon Technologies AG

Inventor： Alexander ROTH ,  Andreas GRASSMANN ,  Juergen HOEGERL ,  Angela KESSLER

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/00 ,  H05K7/10 ,  H01L23/31 ,  H01L23/433 ,  H01L21/56

Abstract: A chip carrier for carrying an electronic chip, wherein the chip carrier comprises a mounting section configured for mounting an electronic chip by sintering, and an encapsulation section configured for being encapsulated by an encapsulant.

公开(公告)号：US20210287964A1

公开(公告)日：2021-09-16

申请号：US17196652

申请日：2021-03-09

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Robert FEHLER ,  Josef HOEGLAUER ,  Angela KESSLER

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

公开(公告)号：US20160035658A1

公开(公告)日：2016-02-04

申请号：US14815367

申请日：2015-07-31

Applicant: Infineon Technologies AG

Inventor： Angela KESSLER ,  Eduard KNAUER ,  Rudolf LEHNER ,  Wolfgang SCHOBER ,  Sigrid SCHULTES

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/36 ,  H01L21/48 ,  H01L23/31 ,  H01L23/492

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5389 ,  H01L2224/32225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device.

Abstract translation: 一种电子设备，包括具有安装表面的载体，安装在所述安装表面上的至少一个电子芯片，安装在所述安装表面上的至少一个电连接结构，至少部分地封装所述载体和所述至少一个电子芯片的密封剂， 并且部分地封装所述至少一个电连接结构，使得所述至少一个电连接结构的表面的一部分暴露于环境;以及安装配置，用于将所述电子设备安装在周边设备。

公开(公告)号：US20240105678A1

公开(公告)日：2024-03-28

申请号：US18243231

申请日：2023-09-07

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Angela KESSLER ,  Thorsten SCHARF

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/19 ,  H01L24/24 ,  H01L25/50 ,  H01L2224/19 ,  H01L2224/24137

Abstract: A chip package is provided. The chip package includes an electrically conductive carrier structure, a first power chip on the carrier structure having a control contact pad and a second power chip on the carrier structure having a control contact pad. The first and second power chips are arranged with their respective control contact pad facing a redistribution layer. A logic chip is arranged with a logic contact pad facing a redistribution layer, wherein the redistribution layer connects the logic contact pad with the respective control pads of the power chips.

公开(公告)号：US20190006260A1

公开(公告)日：2019-01-03

申请号：US16111606

申请日：2018-08-24

Applicant: Infineon Technologies AG

Inventor： Mark PAVIER ,  Wolfram HABLE ,  Angela KESSLER ,  Michael SIELAFF ,  Anton PUGATSCHOW ,  Charles RIMBERT-RIVIERE ,  Marco SOBKOWIAK

IPC: H01L23/373 ,  B60R16/02 ,  H01L21/56 ,  H01L21/48 ,  H01L25/18 ,  H01L23/29 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L23/31

Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.

公开(公告)号：US20250015008A1

公开(公告)日：2025-01-09

申请号：US18764578

申请日：2024-07-05

Applicant: Infineon Technologies AG

Inventor： Mahadi-Ul HASSAN ,  Angela KESSLER ,  Martin Andrew NAVARRE ,  Tobias POLSTER

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065

Abstract: A die embedded package is disclosed. In one example, the die embedded package includes a first bare die and a second bare die, the first bare die being thinner than the second bare die, a first encapsulation material encapsulating the first bare die, wherein the total thickness of the first encapsulation and the first bare die is approximately equal to the thickness of the second bare die. An outer surface of the first encapsulation material and an outer surface of the second bare die are arranged coplanarly. A first and second set of electrically conductive vias electrically contact the first bare die. A third set of electrically conductive vias electrically contacts the second bare die.

公开(公告)号：US20220254696A1

公开(公告)日：2022-08-11

申请号：US17575038

申请日：2022-01-13

Applicant: Infineon Technologies AG

Inventor： Angela KESSLER ,  Kok Yau CHUA ,  Josef HOEGLAUER ,  Chiah Chin LIM ,  Mei Qi TAY

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H01L21/52

Abstract: A package and method of manufacturing is disclosed. In one example, the package which comprises a carrier with at least one component mounted on the carrier. A clip is arranged above the carrier and having a through hole. At least part of at least one of the at least one component and/or at least part of an electrically conductive connection element electrically connecting the at least one component is at least partially positioned inside the through hole.

公开(公告)号：US20170278762A1

公开(公告)日：2017-09-28

申请号：US15468045

申请日：2017-03-23

Applicant: Infineon Technologies AG

Inventor： Angela KESSLER ,  Oliver HAEBERLEN ,  Matteo-Alessandro KUTSCHAK ,  Ralf OTREMBA ,  Petteri PALM ,  Boris PLIKAT ,  Thorsten SCHARF ,  Klaus SCHIESS ,  Fabian SCHNOY ,  Erich SYRI

IPC: H01L21/66 ,  H01L23/498 ,  G01N21/84 ,  H01L23/31

CPC classification number: H01L22/32 ,  G01N21/84 ,  G01N21/95684 ,  G01N2201/12 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/052 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1033

Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.