公开(公告)号：US20150194398A1

公开(公告)日：2015-07-09

申请号：US14662944

申请日：2015-03-19

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。

公开(公告)号：US20130134420A1

公开(公告)日：2013-05-30

申请号：US13750919

申请日：2013-01-25

Applicant: Infineon Technologies AG

Inventor： Alois Gutmann ,  Roland Hampp ,  Scott Jansen

IPC: H01L29/06 ,  H01L29/12

CPC classification number: H01L29/7846 ,  H01L21/76232 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/12 ,  H01L29/78 ,  H01L29/7848

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

公开(公告)号：US20150137309A1

公开(公告)日：2015-05-21

申请号：US14559801

申请日：2014-12-03

Applicant: Infineon Technologies AG

Inventor： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract translation: 公开了制造半导体器件的隔离区域的方法及其结构。 在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。 所述至少一个沟槽包括侧壁，底面，下部和上部。 第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。 第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。 第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。 第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。 第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

公开(公告)号：US08907444B2

公开(公告)日：2014-12-09

申请号：US13750919

申请日：2013-01-25

Applicant: Infineon Technologies AG

Inventor： Alois Gutmann ,  Roland Hampp ,  Scott Jansen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/12

CPC classification number: H01L29/7846 ,  H01L21/76232 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/12 ,  H01L29/78 ,  H01L29/7848

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract translation: 公开了应力诱导结构，方法和材料。 在一个实施例中，隔离区域包括在工件中形成的沟槽的下部中的绝缘材料和设置在绝缘材料上方的沟槽顶部的应力诱导材料。

公开(公告)号：US20140048940A1

公开(公告)日：2014-02-20

申请号：US14060734

申请日：2013-10-23

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。

公开(公告)号：US09373717B2

公开(公告)日：2016-06-21

申请号：US14565243

申请日：2014-12-09

Applicant: Infineon Technologies AG

Inventor： Alois Gutmann ,  Roland Hampp ,  Scott Jansen

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/12

CPC classification number: H01L29/7846 ,  H01L21/76232 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/12 ,  H01L29/78 ,  H01L29/7848

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

公开(公告)号：US20150137253A1

公开(公告)日：2015-05-21

申请号：US14565243

申请日：2014-12-09

Applicant: Infineon Technologies AG

Inventor： Alois Gutmann ,  Roland Hampp ,  Scott Jansen

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/76232 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/12 ,  H01L29/78 ,  H01L29/7848

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract translation: 公开了应力诱导结构，方法和材料。 在一个实施例中，隔离区域包括在工件中形成的沟槽的下部中的绝缘材料和设置在绝缘材料上方的沟槽顶部的应力诱导材料。

公开(公告)号：US09653543B2

公开(公告)日：2017-05-16

申请号：US14559801

申请日：2014-12-03

Applicant: Infineon Technologies AG

Inventor： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/77

CPC classification number: H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

公开(公告)号：US09006898B2

公开(公告)日：2015-04-14

申请号：US14060734

申请日：2013-10-23

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。