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    Controlling LED intensity based on a detected photocurrent value
    1.
    发明授权
    Controlling LED intensity based on a detected photocurrent value 有权

    公开(公告)号：US11057972B1

    公开(公告)日：2021-07-06

    申请号：US16837322

    申请日：2020-04-01

    Applicant: Infineon Technologies AG

    Inventor： Adolfo De Cicco ,  Rosario Chiodo ,  Andrea Logiudice ,  Dietrich Bonart ,  Thomas Gross

    IPC: H05B45/14 ,  H05B45/46 ,  H05B45/345

    Abstract: This disclosure includes systems, methods, and techniques for controlling a plurality of light-emitting diodes (LEDs). For example, a circuit includes a switching device, where the switching device is electrically connected to an LED of the plurality of LEDs, and where the switching device is configured to control whether the LED receives an electrical signal from a power source. Additionally, the circuit includes processing circuitry configured to receive a photocurrent signal indicative of a photocurrent value corresponding to the LED, compare the photocurrent value with a threshold photocurrent value, and control, based on the comparison of the photocurrent value with the threshold photocurrent value, an output current of the LED.

    SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT
    5.
    发明申请
    SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT 有权
    半导体元件的制造方法和半导体元件的制造方法

    公开(公告)号：US20140141608A1

    公开(公告)日：2014-05-22

    申请号：US14166090

    申请日：2014-01-28

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

    Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.

    Abstract translation: 一种制造具有半导体本体的半导体部件的方法，包括提供第一导电型的基板。 在基板上设置第二导电类型的掩埋半导体层。 功能单元半导体层设置在掩埋半导体层上。 至少一个到达衬底的沟槽形成在半导体本体中。 形成绝缘层，其覆盖沟槽的内壁，并使沟槽内部与功能单元半导体层和埋入半导体层电绝缘，绝缘层在沟槽底部的区域中具有至少一个开口。 所述至少一个沟槽填充有第一导电类型的导电半导体材料，其中所述导电半导体材料形成从所述半导体主体的表面到所述衬底的电接触。

    Electrically-Verifiable Fuses and Method of Fuse Verification
    6.
    发明申请
    Electrically-Verifiable Fuses and Method of Fuse Verification 审中-公开

    公开(公告)号：US20190113562A1

    公开(公告)日：2019-04-18

    申请号：US15785773

    申请日：2017-10-17

    Applicant: Infineon Technologies AG

    Inventor： Dietrich Bonart ,  Thomas Gross ,  Franziska Haering

    IPC: G01R31/26 ,  H01L21/66 ,  H01L23/525 ,  G01R31/07

    Abstract: A semiconductor wafer includes a semiconductor substrate having a plurality of die areas separated from one another by dicing areas. Each die area includes one or more metal layers above the semiconductor substrate and a plurality of fuse structures formed in at least one of the one or more metal layers. Each fuse structure includes a fuse area between first and second fuse heads. Each die area also includes a first pair of contacts connected to different areas of the first fuse head of at least some of the fuse structures. The wafer can be singulated along the dicing areas into individual dies. A corresponding method of fuse verification is also provided.

    Semiconductor device having a through contact
    7.
    发明授权
    Semiconductor device having a through contact 有权
    具有通孔的半导体器件

    公开(公告)号：US08941217B2

    公开(公告)日：2015-01-27

    申请号：US14249642

    申请日：2014-04-10

    Applicant: Infineon Technologies AG

    Inventor： Hermann Gruber ,  Thomas Gross ,  Andreas Peter Meiser ,  Markus Zundel

    IPC: H01L29/40 ,  H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side, an active area and a through contact area, the active area including a transistor structure having a control electrode, the through contact area including a semiconductor mesa having insulated sidewalls. The semiconductor device further includes a first metallization on the first side in the active area and a recess extending from the first side into the semiconductor substrate and between the active area and the through contact area and including in the through contact area a horizontally widening portion, the recess being at least partly filled with a conductive material forming a first conductive region in ohmic contact with the semiconductor mesa and the transistor structure. The semiconductor device also includes a control metallization on the second side and in ohmic contact with the semiconductor mesa.

    Abstract translation: 半导体器件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，有源区和贯通接触区，所述有源区包括具有控制电极的晶体管结构，所述贯通接触区包括半导体台面，所述半导体衬底具有 绝缘侧壁。 所述半导体器件还包括在所述有源区域中的第一侧上的第一金属化和从所述第一侧延伸到所述半导体衬底中以及在所述有源区域和所述贯穿接触区域之间并且在所述贯穿接触区域中包括水平扩大部分的凹部， 所述凹部至少部分地填充有形成与所述半导体台面和所述晶体管结构欧姆接触的第一导电区域的导电材料。 半导体器件还包括在第二侧上的控制金属化并与半导体台面欧姆接触。

    Electrically-verifiable fuses and method of fuse verification
    8.
    发明授权
    Electrically-verifiable fuses and method of fuse verification 有权

    公开(公告)号：US10935590B2

    公开(公告)日：2021-03-02

    申请号：US15785773

    申请日：2017-10-17

    Applicant: Infineon Technologies AG

    Inventor： Dietrich Bonart ,  Thomas Gross ,  Franziska Haering

    IPC: G01R31/26 ,  H01L23/525 ,  H01L23/528 ,  H01L21/66 ,  H01L23/522 ,  G01R31/74

    Abstract: A semiconductor wafer includes a semiconductor substrate having a plurality of die areas separated from one another by dicing areas. Each die area includes one or more metal layers above the semiconductor substrate and a plurality of fuse structures formed in at least one of the one or more metal layers. Each fuse structure includes a fuse area between first and second fuse heads. Each die area also includes a first pair of contacts connected to different areas of the first fuse head of at least some of the fuse structures. The wafer can be singulated along the dicing areas into individual dies. A corresponding method of fuse verification is also provided.

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