公开(公告)号：US20230343769A1

公开(公告)日：2023-10-26

申请号：US17728147

申请日：2022-04-25

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Steve Cho ,  Babak Sabi

IPC分类号： H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18

CPC分类号： H01L25/18 ,  H01L21/78 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155

摘要： Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.

公开(公告)号：US10424561B2

公开(公告)日：2019-09-24

申请号：US15863821

申请日：2018-01-05

申请人： Intel Corporation

发明人： Kyu-Oh Lee ,  Islam A. Salama ,  Ram S. Viswanath ,  Robert L. Sankman ,  Babak Sabi ,  Sri Chaitra Jyotsna Chavali

IPC分类号： H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L25/10 ,  H01L23/498 ,  H01L25/065

摘要： An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

公开(公告)号：US20200098725A1

公开(公告)日：2020-03-26

申请号：US16143339

申请日：2018-09-26

申请人： Intel Corporation

发明人： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Gerald S. Pasdast ,  Babak Sabi

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

摘要： Embodiments herein relate to a semiconductor package or a semiconductor package structure that includes an interposer with opposing first and second sides. A memory and a processing unit may be coupled with the second side of the interposer, and the first side of the interposer may be to couple with the substrate. The processing unit and memory may be communicatively coupled with one another and the substrate by the interposer. Other embodiments may be described or claimed.

公开(公告)号：US09865568B2

公开(公告)日：2018-01-09

申请号：US15038008

申请日：2015-06-25

申请人： Intel Corporation

发明人： Kyu-Oh Lee ,  Islam A. Salama ,  Ram S. Viswanath ,  Robert L. Sankman ,  Babak Sabi ,  Sri Chaitra Jyotsna Chavali

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

摘要： Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.