公开(公告)号：US20240419883A1

公开(公告)日：2024-12-19

申请号：US18209434

申请日：2023-06-13

Applicant: Intel Corporation

Inventor： Lei JIANG ,  Daniel CHRISTENSEN ,  Daniel PANTUSO ,  Kambiz KOMEYLI ,  Jeffrey HICKS ,  Manjunath SHAMANNA

IPC: G06F30/392 ,  G06F30/394

Abstract: Disclosed is an integrated circuit with a metallization stack that has thermal tower assemblages formed from wires in two or more metal layers to assist in dissipating heat out of the metallization stack.

公开(公告)号：US20220130803A1

公开(公告)日：2022-04-28

申请号：US17572219

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Brennen K. MUELLER ,  Patrick MORROW ,  Kimin JUN ,  Paul B. FISCHER ,  Daniel PANTUSO

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/84 ,  H01L23/485 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/12

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

公开(公告)号：US20190304784A1

公开(公告)日：2019-10-03

申请号：US15943551

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Chytra PAWASHE ,  Daniel PANTUSO

IPC: H01L21/18 ,  H01L21/20

Abstract: Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20180323174A1

公开(公告)日：2018-11-08

申请号：US15773514

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Brennen K. MUELLER ,  Patrick MORROW ,  Kimin JUN ,  Paul B. FISCHER ,  Daniel PANTUSO

IPC: H01L25/065 ,  H01L27/12 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/76251 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/09181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16141 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/48105 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/014

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.