公开(公告)号：US09960079B2

公开(公告)日：2018-05-01

申请号：US13897202

申请日：2013-05-17

Applicant: Intel Corporation

Inventor： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L21/20 ,  H01L21/768 ,  H01L21/48 ,  H01L23/64 ,  H01L23/66 ,  H05K1/11 ,  H05K1/16 ,  H01L23/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.