公开(公告)号：US11081448B2

公开(公告)日：2021-08-03

申请号：US16474019

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC: H01L23/538 ,  H01L23/52 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US20250112175A1

公开(公告)日：2025-04-03

申请号：US18477638

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jesse C. Jones ,  Yosef Kornbluth ,  Mitchell Page ,  Soham Agarwal ,  Fanyi Zhu ,  Shuren Qu ,  Hanyu Song ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Bai Nie ,  Nicholas Haehn ,  Astitva Tripathi ,  Mohamed R. Saber ,  Sheng Li ,  Pratyush Mishra ,  Benjamin T. Duong ,  Kari Hernandez ,  Praveen Sreeramagiri ,  Yi Li ,  Ibrahim El Khatib ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Haobo Chen ,  Robin Shea McRee ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L25/065

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

公开(公告)号：US20210366835A1

公开(公告)日：2021-11-25

申请号：US17391905

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated. substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US11062933B2

公开(公告)日：2021-07-13

申请号：US16037459

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Jesse C. Jones ,  Gang Duan ,  Yosuke Kanaoka ,  Rahul N. Manepalli

IPC: H01L23/00 ,  H01L21/683 ,  B25B11/00

Abstract: A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.

公开(公告)号：US12087700B2

公开(公告)日：2024-09-10

申请号：US17391905

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0652 ,  H01L23/5221 ,  H01L23/5381 ,  H01L24/16 ,  H01L2224/023 ,  H01L2224/0233 ,  H01L2224/16235

Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US11527484B2

公开(公告)日：2022-12-13

申请号：US17078897

申请日：2020-10-23

Applicant: Intel Corporation

Inventor： Jesse C. Jones ,  Gang Duan ,  Jason Gamba ,  Yosuke Kanaoka ,  Rahul N. Manepalli ,  Vishal Shajan

IPC: H01L23/544 ,  H01L21/762 ,  H01L23/538

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

公开(公告)号：US20200027841A1

公开(公告)日：2020-01-23

申请号：US16037504

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Jesse C. Jones ,  Gang Duan ,  Jason Gamba ,  Yosuke Kanaoka ,  Rahul N. Manepalli ,  Vishal Shajan

IPC: H01L23/544 ,  H01L21/762 ,  H01L23/538

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

公开(公告)号：US20200027775A1

公开(公告)日：2020-01-23

申请号：US16037459

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Jesse C. Jones ,  Gang Duan ,  Yosuke Kanaoka ,  Rahul N. Manepalli

IPC: H01L21/683 ,  B25B11/00

Abstract: A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.

公开(公告)号：US20190333861A1

公开(公告)日：2019-10-31

申请号：US16474019

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manapalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.