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公开(公告)号:US11443970B2
公开(公告)日:2022-09-13
申请号:US16803361
申请日:2020-02-27
Applicant: Intel Corporation
Inventor: Manohar S. Konchady , Tao Wu , Mihir K. Roy , Wei-Lun K. Jen , Yi Li
IPC: H01L21/683 , H01L23/538 , H01L23/498
Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
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公开(公告)号:US20180166294A1
公开(公告)日:2018-06-14
申请号:US15377635
申请日:2016-12-13
Applicant: Intel Corporation
Inventor: Zheng Zhou , Yi Li , Tao Wu , Nikhil Sharma
IPC: H01L21/3105 , H01L21/683 , H01L21/56 , H05B3/22
CPC classification number: H05B3/22 , H01L21/31058 , H01L21/4846 , H01L23/498 , H01L2021/607 , H05B2203/033
Abstract: Embodiments herein relate to methods and apparatus to achieve substantially uniform package thickness after forming a buildup layer on a package substrate of an integrated circuit. Some embodiments include applying a resin to the buildup layer to form a resin layer on top of at least a portion of the buildup layer and substantially evening out the surface formed by the resin layer. Some embodiments include vibrating a hot press onto the top surface of the buildup layer and vibrating the hot press in an ultrasonic and/or a scrubbing motion. Other embodiments may be described and/or claimed.
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公开(公告)号:US20250006609A1
公开(公告)日:2025-01-02
申请号:US18883752
申请日:2024-09-12
Applicant: Intel Corporation
Inventor: Gang Duan , Ibrahim El Khatib , Jesse Cole Jones , Yi Li , Minglu Liu , Robin Shea McRee , Srinivas Venkata Ramanuja Pietambaram , Praveen Sreeramagiri
IPC: H01L23/498 , H01L23/15 , H01L25/065
Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a second CTE different from the first CTE, the first through glass via electrically coupled to the second through glass via.
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公开(公告)号:US20250112175A1
公开(公告)日:2025-04-03
申请号:US18477638
申请日:2023-09-29
Applicant: Intel Corporation
Inventor: Brandon C. Marin , Jesse C. Jones , Yosef Kornbluth , Mitchell Page , Soham Agarwal , Fanyi Zhu , Shuren Qu , Hanyu Song , Srinivas V. Pietambaram , Yonggang Li , Bai Nie , Nicholas Haehn , Astitva Tripathi , Mohamed R. Saber , Sheng Li , Pratyush Mishra , Benjamin T. Duong , Kari Hernandez , Praveen Sreeramagiri , Yi Li , Ibrahim El Khatib , Whitney Bryks , Mahdi Mohammadighaleni , Joshua Stacey , Travis Palmer , Gang Duan , Jeremy Ecton , Suddhasattwa Nad , Haobo Chen , Robin Shea McRee , Mohammad Mamunur Rahman
IPC: H01L23/00 , H01L23/13 , H01L23/15 , H01L25/065
Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.
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公开(公告)号:US20170250150A1
公开(公告)日:2017-08-31
申请号:US15596968
申请日:2017-05-16
Applicant: Intel Corporation
Inventor: Manohar S. KONCHADY , Tao Wu , Mihir K. Roy , Wei-Lun K. Jen , Yi Li
CPC classification number: H01L21/6835 , H01L23/49816 , H01L23/5383 , H01L23/5389 , H01L2221/68345 , H01L2221/68381 , H01L2224/04105 , H01L2224/12105 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/18 , H01L2224/73267 , H01L2924/15192 , H01L2924/15311 , H01L2924/19106
Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
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公开(公告)号:US10957667B2
公开(公告)日:2021-03-23
申请号:US16328135
申请日:2016-10-01
Applicant: Intel Corporation
Inventor: Kyu Oh Lee , Yi Li , Yueli Liu
Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).
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