公开(公告)号：US10727368B2

公开(公告)日：2020-07-28

申请号：US16074758

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Myung Jin Yim ,  Seungjae Lee ,  Sandeep Razdan

IPC: H01L27/15 ,  H01L31/12 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L23/498 ,  H01L25/16 ,  H01L33/58 ,  H01L33/62

Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.

公开(公告)号：US20170288780A1

公开(公告)日：2017-10-05

申请号：US15087344

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Myung Jin Yim ,  Quan A. Tran ,  SeungJae Lee ,  Sandeep Razdan ,  Yigit O. Yilmaz ,  Pradeep Srinivasan ,  Jincheng Wang ,  Ansheng Liu

IPC: H04B10/50 ,  H01S3/10 ,  H01S3/02 ,  H01S3/23

CPC classification number: H04B10/503 ,  H01L2224/73204 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/4087

Abstract: Apparatuses including integrated circuit (IC) optical assemblies and processes for fabrication of IC optical assemblies are disclosed herein. In some embodiments, the IC optical assemblies include an optical transmitter component electrically coupled to a first portion of a packaging substrate. The IC optical assemblies further include an optical transmitter driver component between the optical transmitter component and a second portion of the packaging substrate, wherein a first side of the optical transmitter driver component is electrically coupled to the optical transmitter component. The IC optical assemblies further include a plurality of bumps between a second side of the optical transmitter driver component and proximate the second portion of the packaging substrate, wherein the plurality of bumps are not directly coupled to the optical transmitter driver component.

公开(公告)号：US08987918B2

公开(公告)日：2015-03-24

申请号：US13829483

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及在集成电路（IC）封装组件中具有聚合物芯的互连结构的技术和配置。 在一个实施例中，一种装置包括具有设置在第一管芯的有源侧上的多个晶体管器件的第一管芯和与第一管芯电耦合的多个互连结构，其中多个互连结构中的各个互连结构具有 聚合物芯和设置在聚合物芯上的导电材料，所述导电材料被配置为在第一管芯的晶体管器件和第二管芯之间布置电信号。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10128225B2

公开(公告)日：2018-11-13

申请号：US15436291

申请日：2017-02-17

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L25/065 ,  H01L23/31

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US20170229438A1

公开(公告)日：2017-08-10

申请号：US15436291

申请日：2017-02-17

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L25/065 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L25/50 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US09613934B2

公开(公告)日：2017-04-04

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  C09J9/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US20150162313A1

公开(公告)日：2015-06-11

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及在集成电路（IC）封装组件中具有聚合物芯的互连结构的技术和配置。 在一个实施例中，一种装置包括具有设置在第一管芯的有源侧上的多个晶体管器件的第一管芯和与第一管芯电耦合的多个互连结构，其中多个互连结构中的各个互连结构具有 聚合物芯和设置在聚合物芯上的导电材料，所述导电材料被配置为在第一管芯的晶体管器件和第二管芯之间布置电信号。 可以描述和/或要求保护其他实施例。