公开(公告)号：US08866287B2

公开(公告)日：2014-10-21

申请号：US13631990

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Vinodhkumar Raghunathan

IPC: H01L23/12

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2501 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract translation: 描述了包括基板及其制造的电子组件。 一个组件包括嵌入在多层基板中的电介质层中的管芯，以及嵌入多层基板中的介电层中的电介质区域。 多层基板包括裸片侧和接地侧，第一介电区和电介质层延伸到管芯侧。 多个通孔位于第一电介质区域内，通孔延伸到管芯侧的焊盘。 描述和要求保护其他实施例。

公开(公告)号：US09633837B2

公开(公告)日：2017-04-25

申请号：US14830681

申请日：2015-08-19

Applicant: Intel Corporation

Inventor： Vinodhkumar Raghunathan ,  Ebrahim Andideh

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L21/02271 ,  H01L21/02123 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

公开(公告)号：US09368401B2

公开(公告)日：2016-06-14

申请号：US14501003

申请日：2014-09-29

Applicant: INTEL CORPORATION

Inventor： Weng Hong Teh ,  Vinodhkumar Raghunathan

IPC: H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2501 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract translation: 描述了包括基板及其制造的电子组件。 一个组件包括嵌入在多层基板中的电介质层中的管芯，以及嵌入多层基板中的介电层中的电介质区域。 多层基板包括裸片侧和接地侧，第一介电区和电介质层延伸到管芯侧。 多个通孔位于第一电介质区域内，通孔延伸到管芯侧的焊盘。 描述和要求保护其他实施例。

公开(公告)号：US20150357185A1

公开(公告)日：2015-12-10

申请号：US14830681

申请日：2015-08-19

Applicant: Intel Corporation

Inventor： Vinodhkumar Raghunathan ,  Ebrahim ANDIDEH

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L21/02271 ,  H01L21/02123 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 那些方法可以包括在封装电介质材料上形成CVD电介质材料，然后在CVD电介质材料上形成导电材料。

公开(公告)号：US09748177B2

公开(公告)日：2017-08-29

申请号：US15181226

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Weng Hong Teh ,  Vinodhkumar Raghunathan

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2501 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

公开(公告)号：US09136221B2

公开(公告)日：2015-09-15

申请号：US13630500

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Vinodhkumar Raghunathan ,  Ebrahim Andideh

IPC: H01L23/532 ,  H01L23/538 ,  H01L21/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/02271 ,  H01L21/02123 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 那些方法可以包括在封装电介质材料上形成CVD电介质材料，然后在CVD电介质材料上形成导电材料。