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    High density substrate routing in package
    1.
    发明授权
    High density substrate routing in package 有权

    公开(公告)号：US10861815B2

    公开(公告)日：2020-12-08

    申请号：US16561965

    申请日：2019-09-05

    Applicant: Intel Corporation

    Inventor： Weng Hong Teh ,  Chia-Pin Chiu

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

    High density substrate routing in package
    2.
    发明授权
    High density substrate routing in package 有权

    公开(公告)号：US10199346B2

    公开(公告)日：2019-02-05

    申请号：US15873567

    申请日：2018-01-17

    Applicant: Intel Corporation

    Inventor： Weng Hong Teh ,  Chia-Pin Chiu

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56

    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

    ARRANGEMENT OF THROUGH-HOLE STRUCTURES OF A SEMICONDUCTOR PACKAGE
    5.
    发明申请
    ARRANGEMENT OF THROUGH-HOLE STRUCTURES OF A SEMICONDUCTOR PACKAGE 审中-公开
    半导体封装的通孔结构的布置

    公开(公告)号：US20150217995A1

    公开(公告)日：2015-08-06

    申请号：US14129542

    申请日：2013-09-27

    Applicant: Weng Hong TEH ,  Sarah K. HANEY ,  Chyi Hwang LIM ,  INTEL CORPORATION

    Inventor： Weng Hong Teh ,  Sarah K Haney ,  Chyi Hwang Lim

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81C1/0015 ,  B81B3/0051 ,  B81B2207/015 ,  B81C1/00476 ,  B81C2203/0714 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/73267

    Abstract: A semiconductor package comprising a suspended beam portion including an arrangement of through-hole structures. In an embodiment, a first surface of the suspended beam portion includes edges each defining in part a respective through-hole of a plurality of through-holes extending between the first surface and a second surface. The first surface comprises a plurality of arm portions each located between a respective pair of edge-adjacent edges. The first surface comprises a plurality of node portions each located at a respective junction of three or more of the plurality of arm portions. In another embodiment, for each of the plurality of node portions, a respective total number of arm portions which join one another at the node portion is a number other than four, or two arm portions which join one another at the node portion have respective mid-lines which are oblique to one another.

    Abstract translation: 一种半导体封装，包括包括通孔结构的布置的悬挂梁部分。 在一个实施例中，悬挂梁部分的第一表面包括边缘，每个边缘部分地限定在第一表面和第二表面之间延伸的多个通孔的相应通孔。 第一表面包括多个臂部分，每个臂部分位于相应的一对边缘相邻边缘之间。 第一表面包括多个节点部分，每个节点部分位于多个臂部分中的三个或更多个的相应接合处。 在另一个实施例中，对于多个节点部分中的每个节点部分，在节点部分处彼此连接的臂部分的相应总数是除四个之外的数量，或者在节点部分处彼此连接的两个臂部分分别具有中间 相互倾斜的线条

    Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
    7.
    发明授权
    Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages 有权

    公开(公告)号：US11201128B2

    公开(公告)日：2021-12-14

    申请号：US14998093

    申请日：2015-12-23

    Applicant: Intel Corporation

    Inventor： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

    IPC: H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552

    Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

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