公开(公告)号：US09324672B2

公开(公告)日：2016-04-26

申请号：US12545390

申请日：2009-08-21

申请人： Reza A. Pagaila

发明人： Reza A. Pagaila

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/20 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73259 ,  H01L2224/73277 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a semiconductor device, a plurality of conductive pillars is formed over a temporary carrier. A dual-active sided semiconductor die is mounted over the carrier between the conductive pillars. The semiconductor die has first and second opposing active surfaces with first contact pads on the first active surface and second contact pads on the second active surface. An encapsulant is deposited over the semiconductor die and temporary carrier. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure is electrically connected to the conductive pillars and first contact pads of the dual-active sided semiconductor die. The temporary carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive pillars and second contact pads of the dual-active sided semiconductor die.

摘要翻译： 在半导体器件中，在临时载体上形成多个导电柱。 双主动双面半导体管芯安装在载体之间的导电柱之间。 半导体管芯具有第一和第二相对的有源表面，其中第一有源表面上具有第一接触焊盘，在第二有效表面上具有第二接触焊盘。 密封剂沉积在半导体管芯和临时载体上。 在密封剂的第一表面上形成第一互连结构。 第一互连结构电连接到双主动侧半导体管芯的导电柱和第一接触焊盘。 移除临时载体。 第二互连结构形成在密封剂的与密封剂的第一表面相对的第二表面上。 第二互连结构电连接到双主动侧半导体管芯的导电柱和第二接触焊盘。

公开(公告)号：US09099454B2

公开(公告)日：2015-08-04

申请号：US13964153

申请日：2013-08-12

申请人： Infineon Technologies AG

发明人： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/36 ,  H01L21/56

CPC分类号： H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

摘要： A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

摘要翻译： 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20150041967A1

公开(公告)日：2015-02-12

申请号：US13964153

申请日：2013-08-12

申请人： Infineon Technologies AG

发明人： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

摘要： A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

摘要翻译： 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20120228745A1

公开(公告)日：2012-09-13

申请号：US13183446

申请日：2011-07-15

申请人： Shang-Yi WU ,  Wen-Cheng CHIEN ,  Chia-Lun TSAI ,  Tien-Hao HUANG

发明人： Shang-Yi WU ,  Wen-Cheng CHIEN ,  Chia-Lun TSAI ,  Tien-Hao HUANG

IPC分类号： H01L29/41 ,  H01L21/283

CPC分类号： H01L23/3677 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L33/44 ,  H01L33/642 ,  H01L2224/2401 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2933/0075 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括半导体管芯，导热膜，衬底，多个导电膜图案和至少一个绝缘体。 导热膜设置在半导体管芯的底部。 衬底基本上由导电材料或半导体材料构成。 此外，第一孔设置在基板上并通过基板，并且半导体管芯设置在第一孔中。 导电膜图案设置在基板上，并且不彼此接触。 此外，绝缘体连接在半导体管芯和衬底之间。

公开(公告)号：US20160293582A1

公开(公告)日：2016-10-06

申请号：US15061962

申请日：2016-03-04

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Jun SAGIYA

IPC分类号： H01L25/065 ,  H01L21/78 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73277 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83005

摘要： A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode, and a second semiconductor chip having a third surface facing the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface and a third electrode on the fourth surface. The semiconductor device further includes a metal wire electrically connecting the first and third electrodes, a first insulating layer on the second surface, a first conductive layer that is on the first insulating layer and electrically connected to the second electrode, and a first external terminal electrically connected to the first conductive layer.

摘要翻译： 半导体器件包括第一半导体芯片，第一半导体芯片，第一表面，第一半导体芯片的与第一表面相反侧的第二表面，第一表面上的第一电极，第二表面上的第二电极， 第一接触电连接第一电极和第二电极;以及第二半导体芯片，其具有面向第一表面的第三表面，在第二半导体芯片的与第三表面相反的一侧上的第四表面和在第三表面上的第三电极 第四面。 半导体器件还包括电连接第一和第三电极的金属线，第二表面上的第一绝缘层，位于第一绝缘层上并与第二电极电连接的第一导电层，以及第一外部端子电连接 连接到第一导电层。

公开(公告)号：US08836144B2

公开(公告)日：2014-09-16

申请号：US13846608

申请日：2013-03-18

申请人： Chipmos Technologies Inc.

发明人： Tsung Jen Liao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73277 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

摘要翻译： 本发明提供一种半导体封装结构，其包括管芯，多个接合线，密封剂和多个第一外部端子。 模具具有活性表面和背面。 每个接合线的第一端连接到管芯的后表面，并且与第一端相对的第二端电连接到管芯的有效表面。 密封剂覆盖管芯的背面和接合线，其中每个接合线的一部分从密封剂露出。 第一外部端子设置在密封剂的顶表面上，并且分别覆盖接合线的暴露部分并且电连接到接合线。

公开(公告)号：US20140061899A1

公开(公告)日：2014-03-06

申请号：US13846608

申请日：2013-03-18

申请人： CHIPMOS TECHNOLOGIES INC

发明人： TSUNG JEN LIAO

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73277 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

摘要翻译： 本发明提供一种半导体封装结构，其包括管芯，多个接合线，密封剂和多个第一外部端子。 模具具有活性表面和背面。 每个接合线的第一端连接到管芯的后表面，并且与第一端相对的第二端电连接到管芯的有效表面。 密封剂覆盖管芯的背面和接合线，其中每个接合线的一部分从密封剂露出。 第一外部端子设置在密封剂的顶表面上，并且分别覆盖接合线的暴露部分并且电连接到接合线。

公开(公告)号：US08535961B1

公开(公告)日：2013-09-17

申请号：US12964397

申请日：2010-12-09

申请人： Bob Shih-Wei Kuo ,  Brett Arnold Dunlap ,  David Bolognia

发明人： Bob Shih-Wei Kuo ,  Brett Arnold Dunlap ,  David Bolognia

IPC分类号： H01L21/00

CPC分类号： H01L33/486 ,  H01L21/568 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0753 ,  H01L25/167 ,  H01L33/0079 ,  H01L33/64 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73277 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming a light emitting diode (LED) package includes mounting a LED structure to a carrier, overmolding the LED structure in a package body, backgrinding the package body to expose the LED structure, removing the carrier, and forming a redistribution layer (RDL) buildup structure comprising a RDL circuit pattern coupled to a LED of the LED structure. The LED package is formed without a substrate in one embodiment. By forming the LED package without a substrate, the thickness of the LED package is minimized. Further, by forming the LED package without a substrate, heat removal from the LED is maximized as is electrical performance. Further still, by forming the LED package without a substrate, the fabrication cost of the LED package is minimized.

摘要翻译： 一种形成发光二极管（LED）封装的方法，包括将LED结构安装到载体上，将封装体中的LED结构模制成二次模制，背面研磨封装体以暴露LED结构，去除载体，并形成再分布层（ RDL）积累结构，其包括耦合到LED结构的LED的RDL电路图案。 在一个实施例中，LED封装形成为没有基板。 通过形成没有基板的LED封装，LED封装的厚度最小化。 此外，通过在没有基板的情况下形成LED封装，与电气性能一样，从LED的散热最大化。 此外，通过形成没有基板的LED封装，LED封装的制造成本最小化。

公开(公告)号：US20070152310A1

公开(公告)日：2007-07-05

申请号：US11321856

申请日：2005-12-29

申请人： Philip Osborn ,  Teck-Gyu Kang ,  Ilyas Mohammed

发明人： Philip Osborn ,  Teck-Gyu Kang ,  Ilyas Mohammed

IPC分类号： H01L23/02

CPC分类号： H01L24/73 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/85 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73259 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A microelectronic package including a dielectric element with at least one conductive ground pad. The package may also include a microelectronic element with at least one ground contact exposed at a rear surface of the element. The ground pad and the ground contact are electrically connected to each other by an electrically conducting material.

摘要翻译： 一种微电子封装，其包括具有至少一个导电接地焊盘的电介质元件。 封装还可以包括具有在元件的后表面处暴露的至少一个接地触头的微电子元件。 接地焊盘和接地触头通过导电材料彼此电连接。

公开(公告)号：US07091595B2

公开(公告)日：2006-08-15

申请号：US10985051

申请日：2004-11-10

申请人： Edward Fuergut ,  Hermann Vilsmeier ,  Holger Woerner

发明人： Edward Fuergut ,  Hermann Vilsmeier ,  Holger Woerner

IPC分类号： H01L23/22 ,  H01L23/29

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/19 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/82 ,  H01L24/86 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73277 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to a semiconductor device with a semiconductor chip and a rewiring layer, the semiconductor chip being embedded in a housing plastics composition by its rear side contact. The active top side of the semiconductor chip forms a coplanar overall top side with the top side of the housing plastics composition. The rear side contact is led to the overall top side via a flat conductor sheet tape, so that the rear side contact of the semiconductor chip can be accessed from the overall top side.

摘要翻译： 本发明涉及具有半导体芯片和再布线层的半导体器件，其半导体芯片通过其后侧接触嵌入壳体塑料组合物中。 半导体芯片的有源顶侧与外壳塑料组合物的顶侧形成共面整体顶侧。 后侧接触件通过扁平导体片带被引导到整个顶侧，从而可以从整个顶侧接近半导体芯片的后侧接触。