公开(公告)号：US20200328182A1

公开(公告)日：2020-10-15

申请号：US16915282

申请日：2020-06-29

申请人： Intel IP Corporation

发明人： Bernd WAIDHAS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Thomas WAGNER ,  Stephan Stoeckl ,  Laurent MILLOU

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

摘要： An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US20180331053A1

公开(公告)日：2018-11-15

申请号：US15776474

申请日：2015-12-21

申请人： Intel IP Corporation

发明人： Christian GEISSLER ,  Sven ALBERS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Klaus REINGRUBER ,  Thomas WAGNER ,  Marc DITTES

IPC分类号： H01L23/00

摘要： An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

公开(公告)号：US20200066692A1

公开(公告)日：2020-02-27

申请号：US16344633

申请日：2016-12-14

申请人： INTEL IP CORPORATION

发明人： Andreas WOLTER ,  Bernd WAIDHAS ,  Georg SEIDEMANN ,  Klaus REINGRUBER ,  Thomas WAGNER

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

摘要： Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.

公开(公告)号：US20190043800A1

公开(公告)日：2019-02-07

申请号：US16152221

申请日：2018-10-04

申请人： Intel IP Corporation

发明人： Klaus Jürgen REINGRUBER ,  Sven ALBERS ,  Christian Georg GEISSLER ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Marc DITTES

IPC分类号： H01L23/528 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  C25D5/10 ,  C25D7/12 ,  C25D5/02 ,  H01L23/522 ,  C25D5/48 ,  C25D5/54 ,  H05K1/02

摘要： Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US20210057367A1

公开(公告)日：2021-02-25

申请号：US16635146

申请日：2017-09-29

申请人： Intel IP Corporation

发明人： Gianni SIGNORINI ,  Veronica SCIRIHA ,  Thomas WAGNER

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

摘要： In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

公开(公告)号：US20190393191A1

公开(公告)日：2019-12-26

申请号：US16464213

申请日：2016-12-27

申请人： Intel IP Corporation

发明人： Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Bernd WAIDHAS ,  Thomas WAGNER

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768

摘要： Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.

公开(公告)号：US20190214369A1

公开(公告)日：2019-07-11

申请号：US16325970

申请日：2016-09-28

申请人： Intel IP Corporation

发明人： Georg SEIDEMANN ,  Thomas WAGNER ,  Klaus REINGRUBER ,  Bernd WAIDHAS ,  Andreas WOLTER

IPC分类号： H01L25/065 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00

摘要： In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US20200185490A1

公开(公告)日：2020-06-11

申请号：US16617548

申请日：2017-06-30

申请人： INTEL IP CORPORATION

发明人： Georg Seidemann ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Andreas WOLTER ,  Andreas AUGUSTIN

IPC分类号： H01L49/02 ,  H01L23/64 ,  H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01F17/04

摘要： The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.